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1 /*
2 * ASPEED Coprocessor
3 *
4 * Copyright (C) 2025 ASPEED Technology Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #ifndef ASPEED_COPROCESSOR_H
10 #define ASPEED_COPROCESSOR_H
11
12 #include "qom/object.h"
13 #include "hw/arm/aspeed_soc.h"
14
15 struct AspeedCoprocessorState {
16 DeviceState parent;
17
18 MemoryRegion *memory;
19 MemoryRegion sdram;
20 MemoryRegion *sram;
21 MemoryRegion sram_alias;
22 MemoryRegion uart_alias;
23 Clock *sysclk;
24
25 AspeedTimerCtrlState timerctrl;
26 SerialMM *uart;
27 int uart_dev;
28 };
29
30 #define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
31 OBJECT_DECLARE_TYPE(AspeedCoprocessorState, AspeedCoprocessorClass,
32 ASPEED_COPROCESSOR)
33
34 struct AspeedCoprocessorClass {
35 DeviceClass parent_class;
36
37 /** valid_cpu_types: NULL terminated array of a single CPU type. */
38 const char * const *valid_cpu_types;
39 const hwaddr *memmap;
40 const int *irqmap;
41 };
42
43 struct Aspeed27x0CoprocessorState {
44 AspeedCoprocessorState parent;
45 AspeedINTCState intc[2];
46 UnimplementedDeviceState ipc[2];
47 UnimplementedDeviceState pric[2];
48 UnimplementedDeviceState otp;
49
50 ARMv7MState armv7m;
51
52 /*
53 * SCU, SCUIO and FMC are not owned by this coprocessor: they are
54 * shared with the main PSP SoC, and only aliased into this
55 * coprocessor's own address space here.
56 */
57 MemoryRegion scu_alias;
58 MemoryRegion scuio_alias;
59 MemoryRegion fmc_alias;
60 Aspeed2700SCUState *scu;
61 AspeedSCUState *scuio;
62 AspeedSMCState *fmc;
63 };
64
65 #define TYPE_ASPEED27X0SSP_COPROCESSOR "aspeed27x0ssp-coprocessor"
66 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0CoprocessorState,
67 ASPEED27X0SSP_COPROCESSOR)
68
69 #define TYPE_ASPEED27X0TSP_COPROCESSOR "aspeed27x0tsp-coprocessor"
70 DECLARE_OBJ_CHECKERS(Aspeed27x0CoprocessorState, AspeedCoprocessorClass,
71 ASPEED27X0TSP_COPROCESSOR, TYPE_ASPEED27X0TSP_COPROCESSOR)
72
73 #endif /* ASPEED_COPROCESSOR_H */