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1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/intc/aspeed_intc.h"
19 #include "hw/misc/aspeed_scu.h"
20 #include "hw/adc/aspeed_adc.h"
21 #include "hw/misc/aspeed_sdmc.h"
22 #include "hw/misc/aspeed_xdma.h"
23 #include "hw/timer/aspeed_timer.h"
24 #include "hw/rtc/aspeed_rtc.h"
25 #include "hw/i2c/aspeed_i2c.h"
26 #include "hw/i3c/aspeed_i3c.h"
27 #include "hw/ssi/aspeed_smc.h"
28 #include "hw/misc/aspeed_hace.h"
29 #include "hw/misc/aspeed_sbc.h"
30 #include "hw/misc/aspeed_sli.h"
31 #include "hw/misc/aspeed_pwm.h"
32 #include "hw/watchdog/wdt_aspeed.h"
33 #include "hw/net/ftgmac100.h"
34 #include "target/arm/cpu.h"
35 #include "hw/gpio/aspeed_gpio.h"
36 #include "hw/gpio/aspeed_sgpio.h"
37 #include "hw/sd/aspeed_sdhci.h"
38 #include "hw/usb/hcd-ehci.h"
39 #include "qom/object.h"
40 #include "hw/misc/aspeed_lpc.h"
41 #include "hw/misc/unimp.h"
42 #include "hw/pci-host/aspeed_pcie.h"
43 #include "hw/misc/aspeed_peci.h"
44 #include "hw/fsi/aspeed_apb2opb.h"
45 #include "hw/char/serial-mm.h"
46 #include "hw/intc/arm_gicv3.h"
47 #include "hw/misc/aspeed_ltpi.h"
48 #include "hw/arm/aspeed_ast1700.h"
49
50 #define VBOOTROM_FILE_NAME "ast27x0_bootrom.bin"
51
52 #define ASPEED_SPIS_NUM 3
53 #define ASPEED_SGPIO_NUM 2
54 #define ASPEED_EHCIS_NUM 4
55 #define ASPEED_WDTS_NUM 8
56 #define ASPEED_CPUS_NUM 4
57 #define ASPEED_MACS_NUM 4
58 #define ASPEED_UARTS_NUM 13
59 #define ASPEED_JTAG_NUM 2
60 #define ASPEED_PCIE_NUM 3
61 #define ASPEED_INTC_NUM 2
62 #define ASPEED_IOEXP_NUM 2
63 #define ASPEED_SRAM_NUM 2
64
65 struct AspeedSoCState {
66 DeviceState parent;
67
68 MemoryRegion *memory;
69 MemoryRegion *dram_mr;
70 MemoryRegion dram_container;
71 MemoryRegion sram[ASPEED_SRAM_NUM];
72 MemoryRegion spi_boot_container;
73 MemoryRegion spi_boot;
74 MemoryRegion vbootrom;
75 MemoryRegion pcie_mmio_alias[ASPEED_PCIE_NUM];
76 AddressSpace dram_as;
77 AspeedRtcState rtc;
78 AspeedTimerCtrlState timerctrl;
79 AspeedI2CState i2c;
80 AspeedI3CState i3c;
81 AspeedSCUState scu;
82 AspeedSCUState scuio;
83 AspeedHACEState hace;
84 AspeedXDMAState xdma;
85 AspeedADCState adc;
86 AspeedSMCState fmc;
87 AspeedSMCState spi[ASPEED_SPIS_NUM];
88 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
89 AspeedSBCState sbc;
90 AspeedSLIState sli;
91 AspeedSLIState sliio;
92 UnimplementedDeviceState sbc_unimplemented;
93 AspeedSDMCState sdmc;
94 AspeedPWMState pwm;
95 AspeedWDTState wdt[ASPEED_WDTS_NUM];
96 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
97 AspeedMiiState mii[ASPEED_MACS_NUM];
98 AspeedGPIOState gpio;
99 AspeedGPIOState gpio_1_8v;
100 AspeedSGPIOState sgpiom[ASPEED_SGPIO_NUM];
101 AspeedSDHCIState sdhci;
102 AspeedSDHCIState emmc;
103 AspeedLPCState lpc;
104 AspeedPCIECfgState pcie[ASPEED_PCIE_NUM];
105 AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM];
106 AspeedPECIState peci;
107 SerialMM uart[ASPEED_UARTS_NUM];
108 Clock *sysclk;
109 UnimplementedDeviceState iomem;
110 UnimplementedDeviceState iomem0;
111 UnimplementedDeviceState iomem1;
112 UnimplementedDeviceState video;
113 UnimplementedDeviceState emmc_boot_controller;
114 UnimplementedDeviceState dpmcu;
115 UnimplementedDeviceState espi;
116 UnimplementedDeviceState udc;
117 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
118 AspeedAPB2OPBState fsi[2];
119 AspeedLTPIState ltpi_ctrl[ASPEED_IOEXP_NUM];
120 AspeedAST1700SoCState ioexp[ASPEED_IOEXP_NUM];
121 };
122
123 #define TYPE_ASPEED_SOC "aspeed-soc"
124 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
125
126 struct Aspeed2400SoCState {
127 AspeedSoCState parent;
128
129 ARMCPU cpu[ASPEED_CPUS_NUM];
130 AspeedVICState vic;
131 };
132
133 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
134 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
135
136 struct Aspeed2600SoCState {
137 AspeedSoCState parent;
138
139 A15MPPrivState a7mpcore;
140 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
141 };
142
143 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
144 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
145
146 struct Aspeed27x0SoCState {
147 AspeedSoCState parent;
148
149 ARMCPU cpu[ASPEED_CPUS_NUM];
150 AspeedINTCState intc[ASPEED_INTC_NUM];
151 AspeedINTCState intcioexp[ASPEED_IOEXP_NUM];
152 GICv3State gic;
153 MemoryRegion dram_empty;
154 Aspeed2700SCUState scu;
155 };
156
157 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
158 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
159
160 struct Aspeed10x0SoCState {
161 AspeedSoCState parent;
162
163 ARMv7MState armv7m;
164 };
165
166 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
167 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
168
169 struct AspeedSoCClass {
170 DeviceClass parent_class;
171
172 /** valid_cpu_types: NULL terminated array of a single CPU type. */
173 const char * const *valid_cpu_types;
174 uint32_t silicon_rev;
175 uint64_t sram_size[ASPEED_SRAM_NUM];
176 int pcie_num;
177 int spis_num;
178 int sgpio_num;
179 int ehcis_num;
180 int wdts_num;
181 int macs_num;
182 int uarts_num;
183 int uarts_base;
184 int ioexp_num;
185 const int *irqmap;
186 const hwaddr *memmap;
187 uint32_t num_cpus;
188 bool (*boot_from_emmc)(AspeedSoCState *s);
189 };
190
191 enum {
192 ASPEED_DEV_VBOOTROM,
193 ASPEED_DEV_SPI_BOOT,
194 ASPEED_DEV_IOMEM,
195 ASPEED_DEV_IOMEM0,
196 ASPEED_DEV_IOMEM1,
197 ASPEED_DEV_UART0,
198 ASPEED_DEV_UART1,
199 ASPEED_DEV_UART2,
200 ASPEED_DEV_UART3,
201 ASPEED_DEV_UART4,
202 ASPEED_DEV_UART5,
203 ASPEED_DEV_UART6,
204 ASPEED_DEV_UART7,
205 ASPEED_DEV_UART8,
206 ASPEED_DEV_UART9,
207 ASPEED_DEV_UART10,
208 ASPEED_DEV_UART11,
209 ASPEED_DEV_UART12,
210 ASPEED_DEV_UART13,
211 ASPEED_DEV_VUART,
212 ASPEED_DEV_FMC,
213 ASPEED_DEV_SPI0,
214 ASPEED_DEV_SPI1,
215 ASPEED_DEV_SPI2,
216 ASPEED_DEV_EHCI1,
217 ASPEED_DEV_EHCI2,
218 ASPEED_DEV_EHCI3,
219 ASPEED_DEV_EHCI4,
220 ASPEED_DEV_VIC,
221 ASPEED_DEV_INTC,
222 ASPEED_DEV_INTCIO,
223 ASPEED_DEV_SDMC,
224 ASPEED_DEV_SCU,
225 ASPEED_DEV_ADC,
226 ASPEED_DEV_SBC,
227 ASPEED_DEV_EMMC_BC,
228 ASPEED_DEV_VIDEO,
229 ASPEED_DEV_SRAM0,
230 ASPEED_DEV_SRAM1,
231 ASPEED_DEV_SDHCI,
232 ASPEED_DEV_GPIO,
233 ASPEED_DEV_GPIO_1_8V,
234 ASPEED_DEV_SGPIOM0,
235 ASPEED_DEV_SGPIOM1,
236 ASPEED_DEV_RTC,
237 ASPEED_DEV_TIMER1,
238 ASPEED_DEV_TIMER2,
239 ASPEED_DEV_TIMER3,
240 ASPEED_DEV_TIMER4,
241 ASPEED_DEV_TIMER5,
242 ASPEED_DEV_TIMER6,
243 ASPEED_DEV_TIMER7,
244 ASPEED_DEV_TIMER8,
245 ASPEED_DEV_WDT,
246 ASPEED_DEV_PWM,
247 ASPEED_DEV_LPC,
248 ASPEED_DEV_IBT,
249 ASPEED_DEV_I2C,
250 ASPEED_DEV_PCIE0,
251 ASPEED_DEV_PCIE1,
252 ASPEED_DEV_PCIE2,
253 ASPEED_DEV_PCIE_PHY0,
254 ASPEED_DEV_PCIE_PHY1,
255 ASPEED_DEV_PCIE_PHY2,
256 ASPEED_DEV_PCIE_MMIO0,
257 ASPEED_DEV_PCIE_MMIO1,
258 ASPEED_DEV_PCIE_MMIO2,
259 ASPEED_DEV_PECI,
260 ASPEED_DEV_ETH1,
261 ASPEED_DEV_ETH2,
262 ASPEED_DEV_ETH3,
263 ASPEED_DEV_ETH4,
264 ASPEED_DEV_MII1,
265 ASPEED_DEV_MII2,
266 ASPEED_DEV_MII3,
267 ASPEED_DEV_MII4,
268 ASPEED_DEV_SDRAM,
269 ASPEED_DEV_XDMA,
270 ASPEED_DEV_EMMC,
271 ASPEED_DEV_KCS,
272 ASPEED_DEV_HACE,
273 ASPEED_DEV_DPMCU,
274 ASPEED_DEV_DP,
275 ASPEED_DEV_I3C,
276 ASPEED_DEV_ESPI,
277 ASPEED_DEV_UDC,
278 ASPEED_DEV_JTAG0,
279 ASPEED_DEV_JTAG1,
280 ASPEED_DEV_FSI1,
281 ASPEED_DEV_FSI2,
282 ASPEED_DEV_SCUIO,
283 ASPEED_DEV_SLI,
284 ASPEED_DEV_SLIIO,
285 ASPEED_GIC_DIST,
286 ASPEED_GIC_REDIST,
287 ASPEED_DEV_IPC0,
288 ASPEED_DEV_IPC1,
289 ASPEED_DEV_LTPI_CTRL1,
290 ASPEED_DEV_LTPI_CTRL2,
291 ASPEED_DEV_LTPI_IO0,
292 ASPEED_DEV_LTPI_IO1,
293 ASPEED_DEV_IOEXP0_I2C,
294 ASPEED_DEV_IOEXP1_I2C,
295 ASPEED_DEV_IOEXP0_INTCIO,
296 ASPEED_DEV_IOEXP1_INTCIO,
297 ASPEED_DEV_IOEXP0_I3C,
298 ASPEED_DEV_IOEXP1_I3C,
299 ASPEED_DEV_PRIC0,
300 ASPEED_DEV_PRIC1,
301 ASPEED_DEV_OTP,
302 };
303
304 const char *aspeed_soc_cpu_type(const char * const *valid_cpu_types);
305 bool aspeed_soc_uart_realize(MemoryRegion *memory, SerialMM *smm,
306 const hwaddr addr, Error **errp);
307 void aspeed_soc_uart_set_chr(SerialMM *uart, int dev, int uarts_base,
308 int uarts_num, Chardev *chr);
309 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
310 void aspeed_mmio_map(MemoryRegion *memory, SysBusDevice *dev, int n,
311 hwaddr addr);
312 void aspeed_mmio_map_unimplemented(MemoryRegion *memory, SysBusDevice *dev,
313 const char *name, hwaddr addr,
314 uint64_t size);
315 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
316 unsigned int count, int unit0);
317 void aspeed_write_boot_rom(BlockBackend *blk, hwaddr addr, size_t rom_size,
318 Error **errp);
319 void aspeed_install_boot_rom(AspeedSoCState *soc, BlockBackend *blk,
320 MemoryRegion *boot_rom, uint64_t rom_size);
321 void aspeed_load_vbootrom(AspeedSoCState *soc, const char *bios_name,
322 Error **errp);
323
324 static inline int aspeed_uart_index(int uart_dev)
325 {
326 return uart_dev - ASPEED_DEV_UART0;
327 }
328
329 static inline int aspeed_uart_first(int uarts_base)
330 {
331 return aspeed_uart_index(uarts_base);
332 }
333
334 static inline int aspeed_uart_last(int uarts_base, int uarts_num)
335 {
336 return aspeed_uart_first(uarts_base) + uarts_num - 1;
337 }
338
339 #endif /* ASPEED_SOC_H */