| 1 | /* |
| 2 | * Axiado SoC AX3000 |
| 3 | * |
| 4 | * Author: Kuan-Jui Chiu <kchiu@axiado.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef AXIADO_AX3000_H |
| 10 | #define AXIADO_AX3000_H |
| 11 | |
| 12 | #include "cpu.h" |
| 13 | #include "hw/intc/arm_gicv3_common.h" |
| 14 | #include "hw/char/cadence_uart.h" |
| 15 | #include "hw/misc/axiado_clk.h" |
| 16 | #include "hw/gpio/cadence_gpio.h" |
| 17 | #include "hw/sd/axiado_sdhci.h" |
| 18 | #include "hw/core/sysbus.h" |
| 19 | #include "qemu/units.h" |
| 20 | |
| 21 | #define TYPE_AX3000_SOC "ax3000" |
| 22 | OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC) |
| 23 | |
| 24 | #define AX3000_DRAM0_BASE 0x3C000000 |
| 25 | #define AX3000_DRAM0_SIZE (1088 * MiB) |
| 26 | #define AX3000_DRAM1_BASE 0x400000000 |
| 27 | #define AX3000_DRAM1_SIZE (2 * GiB) |
| 28 | |
| 29 | #define AX3000_GIC_DIST_BASE 0x80300000 |
| 30 | #define AX3000_GIC_DIST_SIZE (64 * KiB) |
| 31 | #define AX3000_GIC_REDIST_BASE 0x80380000 |
| 32 | #define AX3000_GIC_REDIST_SIZE (512 * KiB) |
| 33 | |
| 34 | #define AX3000_UART0_BASE 0x80520000 |
| 35 | #define AX3000_UART1_BASE 0x805a0000 |
| 36 | #define AX3000_UART2_BASE 0x80620000 |
| 37 | #define AX3000_UART3_BASE 0x80520800 |
| 38 | |
| 39 | #define AX3000_SDHCI0_BASE 0x86000000 |
| 40 | #define AX3000_EMMC_PHY_BASE 0x80801C00 |
| 41 | |
| 42 | #define AX3000_GPIO0_BASE 0x80500000 |
| 43 | #define AX3000_GPIO1_BASE 0x80580000 |
| 44 | #define AX3000_GPIO2_BASE 0x80600000 |
| 45 | #define AX3000_GPIO3_BASE 0x80680000 |
| 46 | #define AX3000_GPIO4_BASE 0x80700000 |
| 47 | #define AX3000_GPIO5_BASE 0x80780000 |
| 48 | #define AX3000_GPIO6_BASE 0x80800000 |
| 49 | #define AX3000_GPIO7_BASE 0x80880000 |
| 50 | |
| 51 | #define AX3000_TIMER_CTRL 0x8A020000 |
| 52 | #define AX3000_PLL_BASE 0x80000000 |
| 53 | |
| 54 | enum Ax3000Configuration { |
| 55 | AX3000_NUM_CPUS = 4, |
| 56 | AX3000_NUM_IRQS = 224, |
| 57 | AX3000_NUM_BANKS = 2, |
| 58 | AX3000_NUM_UARTS = 4, |
| 59 | AX3000_NUM_GPIOS = 8, |
| 60 | }; |
| 61 | |
| 62 | typedef struct Ax3000SoCState { |
| 63 | SysBusDevice parent; |
| 64 | |
| 65 | ARMCPU cpu[AX3000_NUM_CPUS]; |
| 66 | GICv3State gic; |
| 67 | MemoryRegion dram[AX3000_NUM_BANKS]; |
| 68 | Ax3000ClkState ax3000_clk; |
| 69 | CadenceUARTState uart[AX3000_NUM_UARTS]; |
| 70 | CadenceGPIOState gpio[AX3000_NUM_GPIOS]; |
| 71 | AxiadoSDHCIState sdhci0; |
| 72 | } Ax3000SoCState; |
| 73 | |
| 74 | typedef struct Ax3000SoCClass { |
| 75 | SysBusDeviceClass parent; |
| 76 | |
| 77 | uint32_t num_cpus; |
| 78 | } Ax3000SoCClass; |
| 79 | |
| 80 | enum Ax3000Irqs { |
| 81 | AX3000_UART0_IRQ = 112, |
| 82 | AX3000_UART1_IRQ = 113, |
| 83 | AX3000_UART2_IRQ = 114, |
| 84 | AX3000_UART3_IRQ = 170, |
| 85 | |
| 86 | AX3000_SDHCI0_IRQ = 123, |
| 87 | |
| 88 | AX3000_GPIO0_IRQ = 183, |
| 89 | AX3000_GPIO1_IRQ = 184, |
| 90 | AX3000_GPIO2_IRQ = 185, |
| 91 | AX3000_GPIO3_IRQ = 186, |
| 92 | AX3000_GPIO4_IRQ = 187, |
| 93 | AX3000_GPIO5_IRQ = 188, |
| 94 | AX3000_GPIO6_IRQ = 189, |
| 95 | AX3000_GPIO7_IRQ = 190, |
| 96 | }; |
| 97 | |
| 98 | #endif /* AXIADO_AX3000_H */ |