| 1 | /* |
| 2 | * |
| 3 | * Copyright (c) 2015 Linaro Limited |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms and conditions of the GNU General Public License, |
| 7 | * version 2 or later, as published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | * |
| 17 | * Define macros useful when building ARM device tree nodes |
| 18 | */ |
| 19 | |
| 20 | #ifndef QEMU_ARM_FDT_H |
| 21 | #define QEMU_ARM_FDT_H |
| 22 | |
| 23 | /* |
| 24 | * These are for GICv2/v3/v4 only; GICv5 encodes the interrupt type in |
| 25 | * the DTB "interrupts" properties differently, using constants that |
| 26 | * match the architectural INTID.Type. In QEMU those are available as |
| 27 | * the GICV5_PPI and GICV5_SPI enum values in arm_gicv5_types.h. |
| 28 | */ |
| 29 | #define GIC_FDT_IRQ_TYPE_SPI 0 |
| 30 | #define GIC_FDT_IRQ_TYPE_PPI 1 |
| 31 | |
| 32 | /* |
| 33 | * The trigger type/level field in the DTB "interrupts" property has |
| 34 | * the same encoding for GICv2/v3/v4 and v5. |
| 35 | */ |
| 36 | #define GIC_FDT_IRQ_FLAGS_EDGE_LO_HI 1 |
| 37 | #define GIC_FDT_IRQ_FLAGS_EDGE_HI_LO 2 |
| 38 | #define GIC_FDT_IRQ_FLAGS_LEVEL_HI 4 |
| 39 | #define GIC_FDT_IRQ_FLAGS_LEVEL_LO 8 |
| 40 | |
| 41 | #define GIC_FDT_IRQ_PPI_CPU_START 8 |
| 42 | #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8 |
| 43 | |
| 44 | #endif |