| 1 | /* |
| 2 | * Freescale i.MX31 SoC emulation |
| 3 | * |
| 4 | * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef FSL_IMX31_H |
| 18 | #define FSL_IMX31_H |
| 19 | |
| 20 | #include "hw/intc/imx_avic.h" |
| 21 | #include "hw/misc/imx31_ccm.h" |
| 22 | #include "hw/char/imx_serial.h" |
| 23 | #include "hw/timer/imx_gpt.h" |
| 24 | #include "hw/timer/imx_epit.h" |
| 25 | #include "hw/i2c/imx_i2c.h" |
| 26 | #include "hw/gpio/imx_gpio.h" |
| 27 | #include "hw/watchdog/wdt_imx2.h" |
| 28 | #include "system/memory.h" |
| 29 | #include "target/arm/cpu.h" |
| 30 | #include "qom/object.h" |
| 31 | |
| 32 | #define TYPE_FSL_IMX31 "fsl-imx31" |
| 33 | OBJECT_DECLARE_SIMPLE_TYPE(FslIMX31State, FSL_IMX31) |
| 34 | |
| 35 | #define FSL_IMX31_NUM_UARTS 2 |
| 36 | #define FSL_IMX31_NUM_EPITS 2 |
| 37 | #define FSL_IMX31_NUM_I2CS 3 |
| 38 | #define FSL_IMX31_NUM_GPIOS 3 |
| 39 | |
| 40 | struct FslIMX31State { |
| 41 | /*< private >*/ |
| 42 | DeviceState parent_obj; |
| 43 | |
| 44 | /*< public >*/ |
| 45 | ARMCPU cpu; |
| 46 | IMXAVICState avic; |
| 47 | IMX31CCMState ccm; |
| 48 | IMXSerialState uart[FSL_IMX31_NUM_UARTS]; |
| 49 | IMXGPTState gpt; |
| 50 | IMXEPITState epit[FSL_IMX31_NUM_EPITS]; |
| 51 | IMXI2CState i2c[FSL_IMX31_NUM_I2CS]; |
| 52 | IMXGPIOState gpio[FSL_IMX31_NUM_GPIOS]; |
| 53 | IMX2WdtState wdt; |
| 54 | MemoryRegion secure_rom; |
| 55 | MemoryRegion rom; |
| 56 | MemoryRegion iram; |
| 57 | MemoryRegion iram_alias; |
| 58 | }; |
| 59 | |
| 60 | #define FSL_IMX31_SECURE_ROM_ADDR 0x00000000 |
| 61 | #define FSL_IMX31_SECURE_ROM_SIZE 0x4000 |
| 62 | #define FSL_IMX31_ROM_ADDR 0x00404000 |
| 63 | #define FSL_IMX31_ROM_SIZE 0x4000 |
| 64 | #define FSL_IMX31_IRAM_ALIAS_ADDR 0x10000000 |
| 65 | #define FSL_IMX31_IRAM_ALIAS_SIZE 0xFFC0000 |
| 66 | #define FSL_IMX31_IRAM_ADDR 0x1FFFC000 |
| 67 | #define FSL_IMX31_IRAM_SIZE 0x4000 |
| 68 | #define FSL_IMX31_I2C1_ADDR 0x43F80000 |
| 69 | #define FSL_IMX31_I2C1_SIZE 0x4000 |
| 70 | #define FSL_IMX31_I2C3_ADDR 0x43F84000 |
| 71 | #define FSL_IMX31_I2C3_SIZE 0x4000 |
| 72 | #define FSL_IMX31_UART1_ADDR 0x43F90000 |
| 73 | #define FSL_IMX31_UART1_SIZE 0x4000 |
| 74 | #define FSL_IMX31_UART2_ADDR 0x43F94000 |
| 75 | #define FSL_IMX31_UART2_SIZE 0x4000 |
| 76 | #define FSL_IMX31_I2C2_ADDR 0x43F98000 |
| 77 | #define FSL_IMX31_I2C2_SIZE 0x4000 |
| 78 | #define FSL_IMX31_CCM_ADDR 0x53F80000 |
| 79 | #define FSL_IMX31_CCM_SIZE 0x4000 |
| 80 | #define FSL_IMX31_GPT_ADDR 0x53F90000 |
| 81 | #define FSL_IMX31_GPT_SIZE 0x4000 |
| 82 | #define FSL_IMX31_EPIT1_ADDR 0x53F94000 |
| 83 | #define FSL_IMX31_EPIT1_SIZE 0x4000 |
| 84 | #define FSL_IMX31_EPIT2_ADDR 0x53F98000 |
| 85 | #define FSL_IMX31_EPIT2_SIZE 0x4000 |
| 86 | #define FSL_IMX31_GPIO3_ADDR 0x53FA4000 |
| 87 | #define FSL_IMX31_GPIO3_SIZE 0x4000 |
| 88 | #define FSL_IMX31_GPIO1_ADDR 0x53FCC000 |
| 89 | #define FSL_IMX31_GPIO1_SIZE 0x4000 |
| 90 | #define FSL_IMX31_GPIO2_ADDR 0x53FD0000 |
| 91 | #define FSL_IMX31_GPIO2_SIZE 0x4000 |
| 92 | #define FSL_IMX31_WDT_ADDR 0x53FDC000 |
| 93 | #define FSL_IMX31_WDT_SIZE 0x4000 |
| 94 | #define FSL_IMX31_AVIC_ADDR 0x68000000 |
| 95 | #define FSL_IMX31_AVIC_SIZE 0x100 |
| 96 | #define FSL_IMX31_SDRAM0_ADDR 0x80000000 |
| 97 | #define FSL_IMX31_SDRAM0_SIZE 0x10000000 |
| 98 | #define FSL_IMX31_SDRAM1_ADDR 0x90000000 |
| 99 | #define FSL_IMX31_SDRAM1_SIZE 0x10000000 |
| 100 | #define FSL_IMX31_FLASH0_ADDR 0xA0000000 |
| 101 | #define FSL_IMX31_FLASH0_SIZE 0x8000000 |
| 102 | #define FSL_IMX31_FLASH1_ADDR 0xA8000000 |
| 103 | #define FSL_IMX31_FLASH1_SIZE 0x8000000 |
| 104 | #define FSL_IMX31_CS2_ADDR 0xB0000000 |
| 105 | #define FSL_IMX31_CS2_SIZE 0x2000000 |
| 106 | #define FSL_IMX31_CS3_ADDR 0xB2000000 |
| 107 | #define FSL_IMX31_CS3_SIZE 0x2000000 |
| 108 | #define FSL_IMX31_CS4_ADDR 0xB4000000 |
| 109 | #define FSL_IMX31_CS4_SIZE 0x2000000 |
| 110 | #define FSL_IMX31_CS5_ADDR 0xB6000000 |
| 111 | #define FSL_IMX31_CS5_SIZE 0x2000000 |
| 112 | #define FSL_IMX31_NAND_ADDR 0xB8000000 |
| 113 | #define FSL_IMX31_NAND_SIZE 0x1000 |
| 114 | |
| 115 | #define FSL_IMX31_EPIT2_IRQ 27 |
| 116 | #define FSL_IMX31_EPIT1_IRQ 28 |
| 117 | #define FSL_IMX31_GPT_IRQ 29 |
| 118 | #define FSL_IMX31_UART2_IRQ 32 |
| 119 | #define FSL_IMX31_UART1_IRQ 45 |
| 120 | #define FSL_IMX31_I2C1_IRQ 10 |
| 121 | #define FSL_IMX31_I2C2_IRQ 4 |
| 122 | #define FSL_IMX31_I2C3_IRQ 3 |
| 123 | #define FSL_IMX31_GPIO1_IRQ 52 |
| 124 | #define FSL_IMX31_GPIO2_IRQ 51 |
| 125 | #define FSL_IMX31_GPIO3_IRQ 56 |
| 126 | |
| 127 | #endif /* FSL_IMX31_H */ |