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1 /*
2 * Copyright (c) 2018 Jean-Christophe Dubois <jcd@tribudubois.net>
3 *
4 * i.MX6ul SoC definitions
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef FSL_IMX6UL_H
18 #define FSL_IMX6UL_H
19
20 #include "hw/cpu/a15mpcore.h"
21 #include "hw/misc/imx6ul_ccm.h"
22 #include "hw/misc/imx6_src.h"
23 #include "hw/misc/imx7_snvs.h"
24 #include "hw/intc/imx_gpcv2.h"
25 #include "hw/watchdog/wdt_imx2.h"
26 #include "hw/gpio/imx_gpio.h"
27 #include "hw/char/imx_serial.h"
28 #include "hw/timer/imx_gpt.h"
29 #include "hw/timer/imx_epit.h"
30 #include "hw/i2c/imx_i2c.h"
31 #include "hw/sd/sdhci.h"
32 #include "hw/ssi/imx_spi.h"
33 #include "hw/net/imx_fec.h"
34 #include "hw/usb/chipidea.h"
35 #include "hw/usb/imx-usb-phy.h"
36 #include "hw/display/imx6ul_lcdif.h"
37 #include "system/memory.h"
38 #include "target/arm/cpu.h"
39 #include "qom/object.h"
40 #include "qemu/units.h"
41
42 #define TYPE_FSL_IMX6UL "fsl-imx6ul"
43 OBJECT_DECLARE_SIMPLE_TYPE(FslIMX6ULState, FSL_IMX6UL)
44
45 enum FslIMX6ULConfiguration {
46 FSL_IMX6UL_NUM_CPUS = 1,
47 FSL_IMX6UL_NUM_UARTS = 8,
48 FSL_IMX6UL_NUM_ETHS = 2,
49 FSL_IMX6UL_ETH_NUM_TX_RINGS = 2,
50 FSL_IMX6UL_NUM_USDHCS = 2,
51 FSL_IMX6UL_NUM_WDTS = 3,
52 FSL_IMX6UL_NUM_GPTS = 2,
53 FSL_IMX6UL_NUM_EPITS = 2,
54 FSL_IMX6UL_NUM_IOMUXCS = 2,
55 FSL_IMX6UL_NUM_GPIOS = 5,
56 FSL_IMX6UL_NUM_I2CS = 4,
57 FSL_IMX6UL_NUM_ECSPIS = 4,
58 FSL_IMX6UL_NUM_ADCS = 2,
59 FSL_IMX6UL_NUM_USB_PHYS = 2,
60 FSL_IMX6UL_NUM_USBS = 2,
61 FSL_IMX6UL_NUM_SAIS = 3,
62 FSL_IMX6UL_NUM_CANS = 2,
63 FSL_IMX6UL_NUM_PWMS = 8,
64 };
65
66 struct FslIMX6ULState {
67 /*< private >*/
68 DeviceState parent_obj;
69
70 /*< public >*/
71 ARMCPU cpu;
72 A15MPPrivState a7mpcore;
73 IMXGPTState gpt[FSL_IMX6UL_NUM_GPTS];
74 IMXEPITState epit[FSL_IMX6UL_NUM_EPITS];
75 IMXGPIOState gpio[FSL_IMX6UL_NUM_GPIOS];
76 IMX6ULCCMState ccm;
77 IMX6SRCState src;
78 IMX7SNVSState snvs;
79 IMXGPCv2State gpcv2;
80 IMXSPIState spi[FSL_IMX6UL_NUM_ECSPIS];
81 IMXI2CState i2c[FSL_IMX6UL_NUM_I2CS];
82 IMXSerialState uart[FSL_IMX6UL_NUM_UARTS];
83 IMXFECState eth[FSL_IMX6UL_NUM_ETHS];
84 SDHCIState usdhc[FSL_IMX6UL_NUM_USDHCS];
85 IMX2WdtState wdt[FSL_IMX6UL_NUM_WDTS];
86 IMXUSBPHYState usbphy[FSL_IMX6UL_NUM_USB_PHYS];
87 ChipideaState usb[FSL_IMX6UL_NUM_USBS];
88 IMX6ULLCDIFState lcdif;
89 MemoryRegion rom;
90 MemoryRegion caam;
91 MemoryRegion ocram;
92 MemoryRegion ocram_alias;
93
94 uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
95 bool phy_connected[FSL_IMX6UL_NUM_ETHS];
96 };
97
98 enum FslIMX6ULMemoryMap {
99 FSL_IMX6UL_MMDC_ADDR = 0x80000000,
100 FSL_IMX6UL_MMDC_SIZE = (2 * GiB),
101
102 FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
103 FSL_IMX6UL_QSPI1_MEM_SIZE = (256 * MiB),
104
105 FSL_IMX6UL_EIM_ALIAS_ADDR = 0x58000000,
106 FSL_IMX6UL_EIM_ALIAS_SIZE = (128 * MiB),
107
108 FSL_IMX6UL_EIM_CS_ADDR = 0x50000000,
109 FSL_IMX6UL_EIM_CS_SIZE = (128 * MiB),
110
111 FSL_IMX6UL_AES_ENCRYPT_ADDR = 0x10000000,
112 FSL_IMX6UL_AES_ENCRYPT_SIZE = (1 * MiB),
113
114 FSL_IMX6UL_QSPI1_RX_ADDR = 0x0C000000,
115 FSL_IMX6UL_QSPI1_RX_SIZE = (32 * MiB),
116
117 /* AIPS-2 Begin */
118 FSL_IMX6UL_UART6_ADDR = 0x021FC000,
119
120 FSL_IMX6UL_I2C4_ADDR = 0x021F8000,
121
122 FSL_IMX6UL_UART5_ADDR = 0x021F4000,
123 FSL_IMX6UL_UART4_ADDR = 0x021F0000,
124 FSL_IMX6UL_UART3_ADDR = 0x021EC000,
125 FSL_IMX6UL_UART2_ADDR = 0x021E8000,
126
127 FSL_IMX6UL_WDOG3_ADDR = 0x021E4000,
128
129 FSL_IMX6UL_QSPI_ADDR = 0x021E0000,
130 FSL_IMX6UL_QSPI_SIZE = 0x500,
131
132 FSL_IMX6UL_SYS_CNT_CTRL_ADDR = 0x021DC000,
133 FSL_IMX6UL_SYS_CNT_CTRL_SIZE = (16 * KiB),
134
135 FSL_IMX6UL_SYS_CNT_CMP_ADDR = 0x021D8000,
136 FSL_IMX6UL_SYS_CNT_CMP_SIZE = (16 * KiB),
137
138 FSL_IMX6UL_SYS_CNT_RD_ADDR = 0x021D4000,
139 FSL_IMX6UL_SYS_CNT_RD_SIZE = (16 * KiB),
140
141 FSL_IMX6UL_TZASC_ADDR = 0x021D0000,
142 FSL_IMX6UL_TZASC_SIZE = (16 * KiB),
143
144 FSL_IMX6UL_PXP_ADDR = 0x021CC000,
145 FSL_IMX6UL_PXP_SIZE = (16 * KiB),
146
147 FSL_IMX6UL_LCDIF_ADDR = 0x021C8000,
148 FSL_IMX6UL_LCDIF_SIZE = (16 * KiB),
149
150 FSL_IMX6UL_CSI_ADDR = 0x021C4000,
151 FSL_IMX6UL_CSI_SIZE = 0x100,
152
153 FSL_IMX6UL_CSU_ADDR = 0x021C0000,
154 FSL_IMX6UL_CSU_SIZE = (16 * KiB),
155
156 FSL_IMX6UL_OCOTP_CTRL_ADDR = 0x021BC000,
157 FSL_IMX6UL_OCOTP_CTRL_SIZE = (4 * KiB),
158
159 FSL_IMX6UL_EIM_ADDR = 0x021B8000,
160 FSL_IMX6UL_EIM_SIZE = 0x100,
161
162 FSL_IMX6UL_SIM2_ADDR = 0x021B4000,
163
164 FSL_IMX6UL_MMDC_CFG_ADDR = 0x021B0000,
165 FSL_IMX6UL_MMDC_CFG_SIZE = (4 * KiB),
166
167 FSL_IMX6UL_ROMCP_ADDR = 0x021AC000,
168 FSL_IMX6UL_ROMCP_SIZE = 0x300,
169
170 FSL_IMX6UL_I2C3_ADDR = 0x021A8000,
171 FSL_IMX6UL_I2C2_ADDR = 0x021A4000,
172 FSL_IMX6UL_I2C1_ADDR = 0x021A0000,
173
174 FSL_IMX6UL_ADC2_ADDR = 0x0219C000,
175 FSL_IMX6UL_ADC1_ADDR = 0x02198000,
176 FSL_IMX6UL_ADCn_SIZE = 0x100,
177
178 FSL_IMX6UL_USDHC2_ADDR = 0x02194000,
179 FSL_IMX6UL_USDHC1_ADDR = 0x02190000,
180
181 FSL_IMX6UL_SIM1_ADDR = 0x0218C000,
182 FSL_IMX6UL_SIMn_SIZE = (16 * KiB),
183
184 FSL_IMX6UL_ENET1_ADDR = 0x02188000,
185
186 FSL_IMX6UL_USBO2_USBMISC_ADDR = 0x02184800,
187 FSL_IMX6UL_USBO2_USBMISC_SIZE = 0x200,
188
189 FSL_IMX6UL_USBO2_USB1_ADDR = 0x02184000,
190 FSL_IMX6UL_USBO2_USB2_ADDR = 0x02184200,
191
192 FSL_IMX6UL_USBO2_PL301_ADDR = 0x02180000,
193 FSL_IMX6UL_USBO2_PL301_SIZE = (16 * KiB),
194
195 FSL_IMX6UL_AIPS2_CFG_ADDR = 0x0217C000,
196 FSL_IMX6UL_AIPS2_CFG_SIZE = 0x100,
197
198 FSL_IMX6UL_CAAM_ADDR = 0x02140000,
199 FSL_IMX6UL_CAAM_SIZE = (16 * KiB),
200
201 FSL_IMX6UL_A7MPCORE_DAP_ADDR = 0x02100000,
202 FSL_IMX6UL_A7MPCORE_DAP_SIZE = (4 * KiB),
203 /* AIPS-2 End */
204
205 /* AIPS-1 Begin */
206 FSL_IMX6UL_PWM8_ADDR = 0x020FC000,
207 FSL_IMX6UL_PWM7_ADDR = 0x020F8000,
208 FSL_IMX6UL_PWM6_ADDR = 0x020F4000,
209 FSL_IMX6UL_PWM5_ADDR = 0x020F0000,
210
211 FSL_IMX6UL_SDMA_ADDR = 0x020EC000,
212 FSL_IMX6UL_SDMA_SIZE = 0x300,
213
214 FSL_IMX6UL_GPT2_ADDR = 0x020E8000,
215
216 FSL_IMX6UL_IOMUXC_GPR_ADDR = 0x020E4000,
217 FSL_IMX6UL_IOMUXC_GPR_SIZE = 0x40,
218
219 FSL_IMX6UL_IOMUXC_ADDR = 0x020E0000,
220 FSL_IMX6UL_IOMUXC_SIZE = 0x700,
221
222 FSL_IMX6UL_GPC_ADDR = 0x020DC000,
223
224 FSL_IMX6UL_SRC_ADDR = 0x020D8000,
225
226 FSL_IMX6UL_EPIT2_ADDR = 0x020D4000,
227 FSL_IMX6UL_EPIT1_ADDR = 0x020D0000,
228
229 FSL_IMX6UL_SNVS_HP_ADDR = 0x020CC000,
230
231 FSL_IMX6UL_USBPHY2_ADDR = 0x020CA000,
232 FSL_IMX6UL_USBPHY1_ADDR = 0x020C9000,
233
234 FSL_IMX6UL_ANALOG_ADDR = 0x020C8000,
235 FSL_IMX6UL_ANALOG_SIZE = 0x300,
236
237 FSL_IMX6UL_CCM_ADDR = 0x020C4000,
238
239 FSL_IMX6UL_WDOG2_ADDR = 0x020C0000,
240 FSL_IMX6UL_WDOG1_ADDR = 0x020BC000,
241
242 FSL_IMX6UL_KPP_ADDR = 0x020B8000,
243 FSL_IMX6UL_KPP_SIZE = 0x10,
244
245 FSL_IMX6UL_ENET2_ADDR = 0x020B4000,
246
247 FSL_IMX6UL_SNVS_LP_ADDR = 0x020B0000,
248 FSL_IMX6UL_SNVS_LP_SIZE = (16 * KiB),
249
250 FSL_IMX6UL_GPIO5_ADDR = 0x020AC000,
251 FSL_IMX6UL_GPIO4_ADDR = 0x020A8000,
252 FSL_IMX6UL_GPIO3_ADDR = 0x020A4000,
253 FSL_IMX6UL_GPIO2_ADDR = 0x020A0000,
254 FSL_IMX6UL_GPIO1_ADDR = 0x0209C000,
255
256 FSL_IMX6UL_GPT1_ADDR = 0x02098000,
257
258 FSL_IMX6UL_CAN2_ADDR = 0x02094000,
259 FSL_IMX6UL_CAN1_ADDR = 0x02090000,
260 FSL_IMX6UL_CANn_SIZE = (4 * KiB),
261
262 FSL_IMX6UL_PWM4_ADDR = 0x0208C000,
263 FSL_IMX6UL_PWM3_ADDR = 0x02088000,
264 FSL_IMX6UL_PWM2_ADDR = 0x02084000,
265 FSL_IMX6UL_PWM1_ADDR = 0x02080000,
266 FSL_IMX6UL_PWMn_SIZE = 0x20,
267
268 FSL_IMX6UL_AIPS1_CFG_ADDR = 0x0207C000,
269 FSL_IMX6UL_AIPS1_CFG_SIZE = (16 * KiB),
270
271 FSL_IMX6UL_BEE_ADDR = 0x02044000,
272 FSL_IMX6UL_BEE_SIZE = (16 * KiB),
273
274 FSL_IMX6UL_TOUCH_CTRL_ADDR = 0x02040000,
275 FSL_IMX6UL_TOUCH_CTRL_SIZE = 0x100,
276
277 FSL_IMX6UL_SPBA_ADDR = 0x0203C000,
278 FSL_IMX6UL_SPBA_SIZE = 0x100,
279
280 FSL_IMX6UL_ASRC_ADDR = 0x02034000,
281 FSL_IMX6UL_ASRC_SIZE = 0x100,
282
283 FSL_IMX6UL_SAI3_ADDR = 0x02030000,
284 FSL_IMX6UL_SAI2_ADDR = 0x0202C000,
285 FSL_IMX6UL_SAI1_ADDR = 0x02028000,
286 FSL_IMX6UL_SAIn_SIZE = 0x200,
287
288 FSL_IMX6UL_UART8_ADDR = 0x02024000,
289 FSL_IMX6UL_UART1_ADDR = 0x02020000,
290 FSL_IMX6UL_UART7_ADDR = 0x02018000,
291
292 FSL_IMX6UL_ECSPI4_ADDR = 0x02014000,
293 FSL_IMX6UL_ECSPI3_ADDR = 0x02010000,
294 FSL_IMX6UL_ECSPI2_ADDR = 0x0200C000,
295 FSL_IMX6UL_ECSPI1_ADDR = 0x02008000,
296
297 FSL_IMX6UL_SPDIF_ADDR = 0x02004000,
298 FSL_IMX6UL_SPDIF_SIZE = 0x100,
299 /* AIPS-1 End */
300
301 FSL_IMX6UL_BCH_ADDR = 0x01808000,
302 FSL_IMX6UL_BCH_SIZE = 0x200,
303
304 FSL_IMX6UL_GPMI_ADDR = 0x01806000,
305 FSL_IMX6UL_GPMI_SIZE = 0x200,
306
307 FSL_IMX6UL_APBH_DMA_ADDR = 0x01804000,
308 FSL_IMX6UL_APBH_DMA_SIZE = (4 * KiB),
309
310 FSL_IMX6UL_A7MPCORE_ADDR = 0x00A00000,
311
312 FSL_IMX6UL_OCRAM_ALIAS_ADDR = 0x00920000,
313 FSL_IMX6UL_OCRAM_ALIAS_SIZE = (384 * KiB),
314
315 FSL_IMX6UL_OCRAM_MEM_ADDR = 0x00900000,
316 FSL_IMX6UL_OCRAM_MEM_SIZE = (128 * KiB),
317
318 FSL_IMX6UL_CAAM_MEM_ADDR = 0x00100000,
319 FSL_IMX6UL_CAAM_MEM_SIZE = (32 * KiB),
320
321 FSL_IMX6UL_ROM_ADDR = 0x00000000,
322 FSL_IMX6UL_ROM_SIZE = (96 * KiB),
323 };
324
325 enum FslIMX6ULIRQs {
326 FSL_IMX6UL_IOMUXC_IRQ = 0,
327 FSL_IMX6UL_DAP_IRQ = 1,
328 FSL_IMX6UL_SDMA_IRQ = 2,
329 FSL_IMX6UL_TSC_IRQ = 3,
330 FSL_IMX6UL_SNVS_IRQ = 4,
331 FSL_IMX6UL_LCDIF_IRQ = 5,
332 FSL_IMX6UL_BEE_IRQ = 6,
333 FSL_IMX6UL_CSI_IRQ = 7,
334 FSL_IMX6UL_PXP_IRQ = 8,
335 FSL_IMX6UL_SCTR1_IRQ = 9,
336 FSL_IMX6UL_SCTR2_IRQ = 10,
337 FSL_IMX6UL_WDOG3_IRQ = 11,
338 FSL_IMX6UL_APBH_DMA_IRQ = 13,
339 FSL_IMX6UL_WEIM_IRQ = 14,
340 FSL_IMX6UL_RAWNAND1_IRQ = 15,
341 FSL_IMX6UL_RAWNAND2_IRQ = 16,
342 FSL_IMX6UL_UART6_IRQ = 17,
343 FSL_IMX6UL_SRTC_IRQ = 19,
344 FSL_IMX6UL_SRTC_SEC_IRQ = 20,
345 FSL_IMX6UL_CSU_IRQ = 21,
346 FSL_IMX6UL_USDHC1_IRQ = 22,
347 FSL_IMX6UL_USDHC2_IRQ = 23,
348 FSL_IMX6UL_SAI3_IRQ = 24,
349 FSL_IMX6UL_SAI32_IRQ = 25,
350
351 FSL_IMX6UL_UART1_IRQ = 26,
352 FSL_IMX6UL_UART2_IRQ = 27,
353 FSL_IMX6UL_UART3_IRQ = 28,
354 FSL_IMX6UL_UART4_IRQ = 29,
355 FSL_IMX6UL_UART5_IRQ = 30,
356
357 FSL_IMX6UL_ECSPI1_IRQ = 31,
358 FSL_IMX6UL_ECSPI2_IRQ = 32,
359 FSL_IMX6UL_ECSPI3_IRQ = 33,
360 FSL_IMX6UL_ECSPI4_IRQ = 34,
361
362 FSL_IMX6UL_I2C4_IRQ = 35,
363 FSL_IMX6UL_I2C1_IRQ = 36,
364 FSL_IMX6UL_I2C2_IRQ = 37,
365 FSL_IMX6UL_I2C3_IRQ = 38,
366
367 FSL_IMX6UL_UART7_IRQ = 39,
368 FSL_IMX6UL_UART8_IRQ = 40,
369
370 FSL_IMX6UL_USB1_IRQ = 43,
371 FSL_IMX6UL_USB2_IRQ = 42,
372 FSL_IMX6UL_USB_PHY1_IRQ = 44,
373 FSL_IMX6UL_USB_PHY2_IRQ = 45,
374
375 FSL_IMX6UL_CAAM_JQ2_IRQ = 46,
376 FSL_IMX6UL_CAAM_ERR_IRQ = 47,
377 FSL_IMX6UL_CAAM_RTIC_IRQ = 48,
378 FSL_IMX6UL_TEMP_IRQ = 49,
379 FSL_IMX6UL_ASRC_IRQ = 50,
380 FSL_IMX6UL_SPDIF_IRQ = 52,
381 FSL_IMX6UL_PMU_REG_IRQ = 54,
382 FSL_IMX6UL_GPT1_IRQ = 55,
383
384 FSL_IMX6UL_EPIT1_IRQ = 56,
385 FSL_IMX6UL_EPIT2_IRQ = 57,
386
387 FSL_IMX6UL_GPIO1_INT7_IRQ = 58,
388 FSL_IMX6UL_GPIO1_INT6_IRQ = 59,
389 FSL_IMX6UL_GPIO1_INT5_IRQ = 60,
390 FSL_IMX6UL_GPIO1_INT4_IRQ = 61,
391 FSL_IMX6UL_GPIO1_INT3_IRQ = 62,
392 FSL_IMX6UL_GPIO1_INT2_IRQ = 63,
393 FSL_IMX6UL_GPIO1_INT1_IRQ = 64,
394 FSL_IMX6UL_GPIO1_INT0_IRQ = 65,
395 FSL_IMX6UL_GPIO1_LOW_IRQ = 66,
396 FSL_IMX6UL_GPIO1_HIGH_IRQ = 67,
397 FSL_IMX6UL_GPIO2_LOW_IRQ = 68,
398 FSL_IMX6UL_GPIO2_HIGH_IRQ = 69,
399 FSL_IMX6UL_GPIO3_LOW_IRQ = 70,
400 FSL_IMX6UL_GPIO3_HIGH_IRQ = 71,
401 FSL_IMX6UL_GPIO4_LOW_IRQ = 72,
402 FSL_IMX6UL_GPIO4_HIGH_IRQ = 73,
403 FSL_IMX6UL_GPIO5_LOW_IRQ = 74,
404 FSL_IMX6UL_GPIO5_HIGH_IRQ = 75,
405
406 FSL_IMX6UL_WDOG1_IRQ = 80,
407 FSL_IMX6UL_WDOG2_IRQ = 81,
408
409 FSL_IMX6UL_KPP_IRQ = 82,
410
411 FSL_IMX6UL_PWM1_IRQ = 83,
412 FSL_IMX6UL_PWM2_IRQ = 84,
413 FSL_IMX6UL_PWM3_IRQ = 85,
414 FSL_IMX6UL_PWM4_IRQ = 86,
415
416 FSL_IMX6UL_CCM1_IRQ = 87,
417 FSL_IMX6UL_CCM2_IRQ = 88,
418
419 FSL_IMX6UL_GPC_IRQ = 89,
420
421 FSL_IMX6UL_SRC_IRQ = 91,
422
423 FSL_IMX6UL_CPU_PERF_IRQ = 94,
424 FSL_IMX6UL_CPU_CTI_IRQ = 95,
425
426 FSL_IMX6UL_SRC_WDOG_IRQ = 96,
427
428 FSL_IMX6UL_SAI1_IRQ = 97,
429 FSL_IMX6UL_SAI2_IRQ = 98,
430
431 FSL_IMX6UL_ADC1_IRQ = 100,
432 FSL_IMX6UL_ADC2_IRQ = 101,
433
434 FSL_IMX6UL_SJC_IRQ = 104,
435
436 FSL_IMX6UL_CAAM_RING0_IRQ = 105,
437 FSL_IMX6UL_CAAM_RING1_IRQ = 106,
438
439 FSL_IMX6UL_QSPI_IRQ = 107,
440
441 FSL_IMX6UL_TZASC_IRQ = 108,
442
443 FSL_IMX6UL_GPT2_IRQ = 109,
444
445 FSL_IMX6UL_CAN1_IRQ = 110,
446 FSL_IMX6UL_CAN2_IRQ = 111,
447
448 FSL_IMX6UL_SIM1_IRQ = 112,
449 FSL_IMX6UL_SIM2_IRQ = 113,
450
451 FSL_IMX6UL_PWM5_IRQ = 114,
452 FSL_IMX6UL_PWM6_IRQ = 115,
453 FSL_IMX6UL_PWM7_IRQ = 116,
454 FSL_IMX6UL_PWM8_IRQ = 117,
455
456 FSL_IMX6UL_ENET1_IRQ = 118,
457 FSL_IMX6UL_ENET1_TIMER_IRQ = 119,
458 FSL_IMX6UL_ENET2_IRQ = 120,
459 FSL_IMX6UL_ENET2_TIMER_IRQ = 121,
460
461 FSL_IMX6UL_PMU_CORE_IRQ = 127,
462 FSL_IMX6UL_MAX_IRQ = 128,
463 };
464
465 #endif /* FSL_IMX6UL_H */