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1 /*
2 * i.MX 8MM SoC Definitions
3 *
4 * Copyright (c) 2025, NXP Semiconductors
5 * Author: Gaurav Sharma <gaurav.sharma_7@nxp.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0-or-later
8 */
9
10 #ifndef FSL_IMX8MM_H
11 #define FSL_IMX8MM_H
12
13 #include "cpu.h"
14 #include "hw/char/imx_serial.h"
15 #include "hw/gpio/imx_gpio.h"
16 #include "hw/i2c/imx_i2c.h"
17 #include "hw/intc/arm_gicv3_common.h"
18 #include "hw/misc/imx7_snvs.h"
19 #include "hw/misc/imx8mp_analog.h"
20 #include "hw/misc/imx8mp_ccm.h"
21 #include "hw/net/imx_fec.h"
22 #include "hw/core/or-irq.h"
23 #include "hw/pci-host/designware.h"
24 #include "hw/pci-host/fsl_imx8m_phy.h"
25 #include "hw/sd/sdhci.h"
26 #include "hw/ssi/imx_spi.h"
27 #include "hw/timer/imx_gpt.h"
28 #include "hw/usb/hcd-dwc3.h"
29 #include "hw/watchdog/wdt_imx2.h"
30 #include "qom/object.h"
31 #include "qemu/units.h"
32
33 #define TYPE_FSL_IMX8MM "fsl-imx8mm"
34 OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM)
35
36 #define FSL_IMX8MM_RAM_START 0x40000000
37 #define FSL_IMX8MM_RAM_SIZE_MAX (4 * GiB)
38
39 enum FslImx8mmConfiguration {
40 FSL_IMX8MM_NUM_CPUS = 4,
41 FSL_IMX8MM_NUM_ECSPIS = 3,
42 FSL_IMX8MM_NUM_GPIOS = 5,
43 FSL_IMX8MM_NUM_GPTS = 6,
44 FSL_IMX8MM_NUM_I2CS = 4,
45 FSL_IMX8MM_NUM_IRQS = 128,
46 FSL_IMX8MM_NUM_UARTS = 4,
47 FSL_IMX8MM_NUM_USBS = 2,
48 FSL_IMX8MM_NUM_USDHCS = 3,
49 FSL_IMX8MM_NUM_WDTS = 3,
50 };
51
52 struct FslImx8mmState {
53 SysBusDevice parent_obj;
54
55 ARMCPU cpu[FSL_IMX8MM_NUM_CPUS];
56 GICv3State gic;
57 IMXGPTState gpt[FSL_IMX8MM_NUM_GPTS];
58 IMXGPIOState gpio[FSL_IMX8MM_NUM_GPIOS];
59 IMX8MPCCMState ccm;
60 IMX8MPAnalogState analog;
61 IMX7SNVSState snvs;
62 IMXSPIState spi[FSL_IMX8MM_NUM_ECSPIS];
63 IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS];
64 IMXSerialState uart[FSL_IMX8MM_NUM_UARTS];
65 MemoryRegion ocram;
66 IMXFECState enet;
67 SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS];
68 IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS];
69 USBDWC3 usb[FSL_IMX8MM_NUM_USBS];
70 DesignwarePCIEHost pcie;
71 FslImx8mPciePhyState pcie_phy;
72 OrIRQState gpt5_gpt6_irq;
73
74 uint32_t phy_num;
75 bool phy_connected;
76 };
77
78 enum FslImx8mmMemoryRegions {
79 FSL_IMX8MM_A53_DAP,
80 FSL_IMX8MM_AIPS1_CONFIGURATION,
81 FSL_IMX8MM_AIPS2_CONFIGURATION,
82 FSL_IMX8MM_AIPS3_CONFIGURATION,
83 FSL_IMX8MM_AIPS4_CONFIGURATION,
84 FSL_IMX8MM_ANA_OSC,
85 FSL_IMX8MM_ANA_PLL,
86 FSL_IMX8MM_ANA_TSENSOR,
87 FSL_IMX8MM_APBH_DMA,
88 FSL_IMX8MM_BOOT_ROM,
89 FSL_IMX8MM_BOOT_ROM_PROTECTED,
90 FSL_IMX8MM_CAAM,
91 FSL_IMX8MM_CAAM_MEM,
92 FSL_IMX8MM_CCM,
93 FSL_IMX8MM_CSU,
94 FSL_IMX8MM_DDR_CTL,
95 FSL_IMX8MM_DDR_PERF_MON,
96 FSL_IMX8MM_DDR_PHY,
97 FSL_IMX8MM_DDR_PHY_BROADCAST,
98 FSL_IMX8MM_ECSPI1,
99 FSL_IMX8MM_ECSPI2,
100 FSL_IMX8MM_ECSPI3,
101 FSL_IMX8MM_ENET1,
102 FSL_IMX8MM_GIC_DIST,
103 FSL_IMX8MM_GIC_REDIST,
104 FSL_IMX8MM_GPC,
105 FSL_IMX8MM_GPIO1,
106 FSL_IMX8MM_GPIO2,
107 FSL_IMX8MM_GPIO3,
108 FSL_IMX8MM_GPIO4,
109 FSL_IMX8MM_GPIO5,
110 FSL_IMX8MM_GPT1,
111 FSL_IMX8MM_GPT2,
112 FSL_IMX8MM_GPT3,
113 FSL_IMX8MM_GPT4,
114 FSL_IMX8MM_GPT5,
115 FSL_IMX8MM_GPT6,
116 FSL_IMX8MM_GPU2D,
117 FSL_IMX8MM_I2C1,
118 FSL_IMX8MM_I2C2,
119 FSL_IMX8MM_I2C3,
120 FSL_IMX8MM_I2C4,
121 FSL_IMX8MM_INTERCONNECT,
122 FSL_IMX8MM_IOMUXC,
123 FSL_IMX8MM_IOMUXC_GPR,
124 FSL_IMX8MM_MEDIA_BLK_CTL,
125 FSL_IMX8MM_LCDIF,
126 FSL_IMX8MM_MIPI_CSI,
127 FSL_IMX8MM_MIPI_DSI,
128 FSL_IMX8MM_MU_A,
129 FSL_IMX8MM_MU_B,
130 FSL_IMX8MM_OCOTP_CTRL,
131 FSL_IMX8MM_OCRAM,
132 FSL_IMX8MM_OCRAM_S,
133 FSL_IMX8MM_PCIE1,
134 FSL_IMX8MM_PCIE1_MEM,
135 FSL_IMX8MM_PCIE_PHY1,
136 FSL_IMX8MM_PERFMON1,
137 FSL_IMX8MM_PERFMON2,
138 FSL_IMX8MM_PWM1,
139 FSL_IMX8MM_PWM2,
140 FSL_IMX8MM_PWM3,
141 FSL_IMX8MM_PWM4,
142 FSL_IMX8MM_QOSC,
143 FSL_IMX8MM_QSPI,
144 FSL_IMX8MM_QSPI1_RX_BUFFER,
145 FSL_IMX8MM_QSPI1_TX_BUFFER,
146 FSL_IMX8MM_QSPI_MEM,
147 FSL_IMX8MM_RAM,
148 FSL_IMX8MM_RDC,
149 FSL_IMX8MM_SAI1,
150 FSL_IMX8MM_SAI2,
151 FSL_IMX8MM_SAI3,
152 FSL_IMX8MM_SAI5,
153 FSL_IMX8MM_SAI6,
154 FSL_IMX8MM_SDMA1,
155 FSL_IMX8MM_SDMA2,
156 FSL_IMX8MM_SDMA3,
157 FSL_IMX8MM_SEMAPHORE1,
158 FSL_IMX8MM_SEMAPHORE2,
159 FSL_IMX8MM_SEMAPHORE_HS,
160 FSL_IMX8MM_SNVS_HP,
161 FSL_IMX8MM_SPBA1,
162 FSL_IMX8MM_SRC,
163 FSL_IMX8MM_SYSCNT_CMP,
164 FSL_IMX8MM_SYSCNT_CTRL,
165 FSL_IMX8MM_SYSCNT_RD,
166 FSL_IMX8MM_TCM_DTCM,
167 FSL_IMX8MM_TCM_ITCM,
168 FSL_IMX8MM_TZASC,
169 FSL_IMX8MM_UART1,
170 FSL_IMX8MM_UART2,
171 FSL_IMX8MM_UART3,
172 FSL_IMX8MM_UART4,
173 FSL_IMX8MM_USB1,
174 FSL_IMX8MM_USB2,
175 FSL_IMX8MM_USB1_OTG,
176 FSL_IMX8MM_USB2_OTG,
177 FSL_IMX8MM_USDHC1,
178 FSL_IMX8MM_USDHC2,
179 FSL_IMX8MM_USDHC3,
180 FSL_IMX8MM_VPU,
181 FSL_IMX8MM_VPU_BLK_CTRL,
182 FSL_IMX8MM_VPU_G1_DECODER,
183 FSL_IMX8MM_VPU_G2_DECODER,
184 FSL_IMX8MM_WDOG1,
185 FSL_IMX8MM_WDOG2,
186 FSL_IMX8MM_WDOG3,
187 };
188
189 enum FslImx8mmIrqs {
190 FSL_IMX8MM_USDHC1_IRQ = 22,
191 FSL_IMX8MM_USDHC2_IRQ = 23,
192 FSL_IMX8MM_USDHC3_IRQ = 24,
193
194 FSL_IMX8MM_UART1_IRQ = 26,
195 FSL_IMX8MM_UART2_IRQ = 27,
196 FSL_IMX8MM_UART3_IRQ = 28,
197 FSL_IMX8MM_UART4_IRQ = 29,
198
199 FSL_IMX8MM_ECSPI1_IRQ = 31,
200 FSL_IMX8MM_ECSPI2_IRQ = 32,
201 FSL_IMX8MM_ECSPI3_IRQ = 33,
202
203 FSL_IMX8MM_I2C1_IRQ = 35,
204 FSL_IMX8MM_I2C2_IRQ = 36,
205 FSL_IMX8MM_I2C3_IRQ = 37,
206 FSL_IMX8MM_I2C4_IRQ = 38,
207
208 FSL_IMX8MM_USB1_IRQ = 40,
209 FSL_IMX8MM_USB2_IRQ = 41,
210
211 FSL_IMX8MM_GPT1_IRQ = 55,
212 FSL_IMX8MM_GPT2_IRQ = 54,
213 FSL_IMX8MM_GPT3_IRQ = 53,
214 FSL_IMX8MM_GPT4_IRQ = 52,
215 FSL_IMX8MM_GPT5_GPT6_IRQ = 51,
216
217 FSL_IMX8MM_GPIO1_LOW_IRQ = 64,
218 FSL_IMX8MM_GPIO1_HIGH_IRQ = 65,
219 FSL_IMX8MM_GPIO2_LOW_IRQ = 66,
220 FSL_IMX8MM_GPIO2_HIGH_IRQ = 67,
221 FSL_IMX8MM_GPIO3_LOW_IRQ = 68,
222 FSL_IMX8MM_GPIO3_HIGH_IRQ = 69,
223 FSL_IMX8MM_GPIO4_LOW_IRQ = 70,
224 FSL_IMX8MM_GPIO4_HIGH_IRQ = 71,
225 FSL_IMX8MM_GPIO5_LOW_IRQ = 72,
226 FSL_IMX8MM_GPIO5_HIGH_IRQ = 73,
227
228 FSL_IMX8MM_WDOG1_IRQ = 78,
229 FSL_IMX8MM_WDOG2_IRQ = 79,
230 FSL_IMX8MM_WDOG3_IRQ = 10,
231
232 FSL_IMX8MM_ENET1_MAC_IRQ = 118,
233 FSL_IMX6_ENET1_MAC_1588_IRQ = 121,
234
235 FSL_IMX8MM_PCI_INTA_IRQ = 122,
236 FSL_IMX8MM_PCI_INTB_IRQ = 123,
237 FSL_IMX8MM_PCI_INTC_IRQ = 124,
238 FSL_IMX8MM_PCI_INTD_IRQ = 125,
239 FSL_IMX8MM_PCI_MSI_IRQ = 127,
240 };
241
242 #endif /* FSL_IMX8MM_H */