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1 /*
2 * i.MX 8M Plus SoC Definitions
3 *
4 * Copyright (c) 2024, Bernhard Beschow <shentey@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #ifndef FSL_IMX8MP_H
10 #define FSL_IMX8MP_H
11
12 #include "target/arm/cpu.h"
13 #include "hw/char/imx_serial.h"
14 #include "hw/gpio/imx_gpio.h"
15 #include "hw/i2c/imx_i2c.h"
16 #include "hw/intc/arm_gicv3_common.h"
17 #include "hw/misc/imx7_snvs.h"
18 #include "hw/misc/imx8mp_analog.h"
19 #include "hw/misc/imx8mp_ccm.h"
20 #include "hw/net/flexcan.h"
21 #include "hw/net/imx_fec.h"
22 #include "hw/core/or-irq.h"
23 #include "hw/pci-host/designware.h"
24 #include "hw/pci-host/fsl_imx8m_phy.h"
25 #include "hw/sd/sdhci.h"
26 #include "hw/ssi/imx_spi.h"
27 #include "hw/timer/imx_gpt.h"
28 #include "hw/usb/hcd-dwc3.h"
29 #include "hw/watchdog/wdt_imx2.h"
30 #include "hw/core/sysbus.h"
31 #include "qom/object.h"
32 #include "qemu/units.h"
33
34 #define TYPE_FSL_IMX8MP "fsl-imx8mp"
35 OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mpState, FSL_IMX8MP)
36
37 #define FSL_IMX8MP_RAM_START 0x40000000
38 #define FSL_IMX8MP_RAM_SIZE_MAX (8 * GiB)
39
40 enum FslImx8mpConfiguration {
41 FSL_IMX8MP_NUM_CANS = 2,
42 FSL_IMX8MP_NUM_CPUS = 4,
43 FSL_IMX8MP_NUM_ECSPIS = 3,
44 FSL_IMX8MP_NUM_GPIOS = 5,
45 FSL_IMX8MP_NUM_GPTS = 6,
46 FSL_IMX8MP_NUM_I2CS = 6,
47 FSL_IMX8MP_NUM_IRQS = 160,
48 FSL_IMX8MP_NUM_UARTS = 4,
49 FSL_IMX8MP_NUM_USBS = 2,
50 FSL_IMX8MP_NUM_USDHCS = 3,
51 FSL_IMX8MP_NUM_WDTS = 3,
52 };
53
54 struct FslImx8mpState {
55 SysBusDevice parent_obj;
56
57 ARMCPU cpu[FSL_IMX8MP_NUM_CPUS];
58 GICv3State gic;
59 IMXGPTState gpt[FSL_IMX8MP_NUM_GPTS];
60 IMXGPIOState gpio[FSL_IMX8MP_NUM_GPIOS];
61 IMX8MPCCMState ccm;
62 IMX8MPAnalogState analog;
63 IMX7SNVSState snvs;
64 IMXSPIState spi[FSL_IMX8MP_NUM_ECSPIS];
65 IMXI2CState i2c[FSL_IMX8MP_NUM_I2CS];
66 IMXSerialState uart[FSL_IMX8MP_NUM_UARTS];
67 IMXFECState enet;
68 SDHCIState usdhc[FSL_IMX8MP_NUM_USDHCS];
69 IMX2WdtState wdt[FSL_IMX8MP_NUM_WDTS];
70 USBDWC3 usb[FSL_IMX8MP_NUM_USBS];
71 DesignwarePCIEHost pcie;
72 FslImx8mPciePhyState pcie_phy;
73 FlexcanState flexcan[FSL_IMX8MP_NUM_CANS];
74 OrIRQState gpt5_gpt6_irq;
75 MemoryRegion ocram;
76
77 uint32_t phy_num;
78 bool phy_connected;
79
80 CanBusState *canbus[FSL_IMX8MP_NUM_CANS];
81 };
82
83 enum FslImx8mpMemoryRegions {
84 FSL_IMX8MP_A53_DAP,
85 FSL_IMX8MP_AIPS1_CONFIGURATION,
86 FSL_IMX8MP_AIPS2_CONFIGURATION,
87 FSL_IMX8MP_AIPS3_CONFIGURATION,
88 FSL_IMX8MP_AIPS4_CONFIGURATION,
89 FSL_IMX8MP_AIPS5_CONFIGURATION,
90 FSL_IMX8MP_ANA_OSC,
91 FSL_IMX8MP_ANA_PLL,
92 FSL_IMX8MP_ANA_TSENSOR,
93 FSL_IMX8MP_APBH_DMA,
94 FSL_IMX8MP_ASRC,
95 FSL_IMX8MP_AUDIO_BLK_CTRL,
96 FSL_IMX8MP_AUDIO_DSP,
97 FSL_IMX8MP_AUDIO_XCVR_RX,
98 FSL_IMX8MP_AUD_IRQ_STEER,
99 FSL_IMX8MP_BOOT_ROM,
100 FSL_IMX8MP_BOOT_ROM_PROTECTED,
101 FSL_IMX8MP_CAAM,
102 FSL_IMX8MP_CAAM_MEM,
103 FSL_IMX8MP_CCM,
104 FSL_IMX8MP_CSU,
105 FSL_IMX8MP_DDR_BLK_CTRL,
106 FSL_IMX8MP_DDR_CTL,
107 FSL_IMX8MP_DDR_PERF_MON,
108 FSL_IMX8MP_DDR_PHY,
109 FSL_IMX8MP_DDR_PHY_BROADCAST,
110 FSL_IMX8MP_ECSPI1,
111 FSL_IMX8MP_ECSPI2,
112 FSL_IMX8MP_ECSPI3,
113 FSL_IMX8MP_EDMA_CHANNELS,
114 FSL_IMX8MP_EDMA_MANAGEMENT_PAGE,
115 FSL_IMX8MP_ENET1,
116 FSL_IMX8MP_ENET2_TSN,
117 FSL_IMX8MP_FLEXCAN1,
118 FSL_IMX8MP_FLEXCAN2,
119 FSL_IMX8MP_GIC_DIST,
120 FSL_IMX8MP_GIC_REDIST,
121 FSL_IMX8MP_GPC,
122 FSL_IMX8MP_GPIO1,
123 FSL_IMX8MP_GPIO2,
124 FSL_IMX8MP_GPIO3,
125 FSL_IMX8MP_GPIO4,
126 FSL_IMX8MP_GPIO5,
127 FSL_IMX8MP_GPT1,
128 FSL_IMX8MP_GPT2,
129 FSL_IMX8MP_GPT3,
130 FSL_IMX8MP_GPT4,
131 FSL_IMX8MP_GPT5,
132 FSL_IMX8MP_GPT6,
133 FSL_IMX8MP_GPU2D,
134 FSL_IMX8MP_GPU3D,
135 FSL_IMX8MP_HDMI_TX,
136 FSL_IMX8MP_HDMI_TX_AUDLNK_MSTR,
137 FSL_IMX8MP_HSIO_BLK_CTL,
138 FSL_IMX8MP_I2C1,
139 FSL_IMX8MP_I2C2,
140 FSL_IMX8MP_I2C3,
141 FSL_IMX8MP_I2C4,
142 FSL_IMX8MP_I2C5,
143 FSL_IMX8MP_I2C6,
144 FSL_IMX8MP_INTERCONNECT,
145 FSL_IMX8MP_IOMUXC,
146 FSL_IMX8MP_IOMUXC_GPR,
147 FSL_IMX8MP_IPS_DEWARP,
148 FSL_IMX8MP_ISI,
149 FSL_IMX8MP_ISP1,
150 FSL_IMX8MP_ISP2,
151 FSL_IMX8MP_LCDIF1,
152 FSL_IMX8MP_LCDIF2,
153 FSL_IMX8MP_MEDIA_BLK_CTL,
154 FSL_IMX8MP_MIPI_CSI1,
155 FSL_IMX8MP_MIPI_CSI2,
156 FSL_IMX8MP_MIPI_DSI1,
157 FSL_IMX8MP_MU_1_A,
158 FSL_IMX8MP_MU_1_B,
159 FSL_IMX8MP_MU_2_A,
160 FSL_IMX8MP_MU_2_B,
161 FSL_IMX8MP_MU_3_A,
162 FSL_IMX8MP_MU_3_B,
163 FSL_IMX8MP_NPU,
164 FSL_IMX8MP_OCOTP_CTRL,
165 FSL_IMX8MP_OCRAM,
166 FSL_IMX8MP_OCRAM_S,
167 FSL_IMX8MP_PCIE1,
168 FSL_IMX8MP_PCIE1_MEM,
169 FSL_IMX8MP_PCIE_PHY1,
170 FSL_IMX8MP_PDM,
171 FSL_IMX8MP_PERFMON1,
172 FSL_IMX8MP_PERFMON2,
173 FSL_IMX8MP_PWM1,
174 FSL_IMX8MP_PWM2,
175 FSL_IMX8MP_PWM3,
176 FSL_IMX8MP_PWM4,
177 FSL_IMX8MP_QOSC,
178 FSL_IMX8MP_QSPI,
179 FSL_IMX8MP_QSPI1_RX_BUFFER,
180 FSL_IMX8MP_QSPI1_TX_BUFFER,
181 FSL_IMX8MP_QSPI_MEM,
182 FSL_IMX8MP_RAM,
183 FSL_IMX8MP_RDC,
184 FSL_IMX8MP_SAI1,
185 FSL_IMX8MP_SAI2,
186 FSL_IMX8MP_SAI3,
187 FSL_IMX8MP_SAI5,
188 FSL_IMX8MP_SAI6,
189 FSL_IMX8MP_SAI7,
190 FSL_IMX8MP_SDMA1,
191 FSL_IMX8MP_SDMA2,
192 FSL_IMX8MP_SDMA3,
193 FSL_IMX8MP_SEMAPHORE1,
194 FSL_IMX8MP_SEMAPHORE2,
195 FSL_IMX8MP_SEMAPHORE_HS,
196 FSL_IMX8MP_SNVS_HP,
197 FSL_IMX8MP_SPBA1,
198 FSL_IMX8MP_SPBA2,
199 FSL_IMX8MP_SRC,
200 FSL_IMX8MP_SYSCNT_CMP,
201 FSL_IMX8MP_SYSCNT_CTRL,
202 FSL_IMX8MP_SYSCNT_RD,
203 FSL_IMX8MP_TCM_DTCM,
204 FSL_IMX8MP_TCM_ITCM,
205 FSL_IMX8MP_TZASC,
206 FSL_IMX8MP_UART1,
207 FSL_IMX8MP_UART2,
208 FSL_IMX8MP_UART3,
209 FSL_IMX8MP_UART4,
210 FSL_IMX8MP_USB1,
211 FSL_IMX8MP_USB2,
212 FSL_IMX8MP_USB1_DEV,
213 FSL_IMX8MP_USB2_DEV,
214 FSL_IMX8MP_USB1_OTG,
215 FSL_IMX8MP_USB2_OTG,
216 FSL_IMX8MP_USB1_GLUE,
217 FSL_IMX8MP_USB2_GLUE,
218 FSL_IMX8MP_USDHC1,
219 FSL_IMX8MP_USDHC2,
220 FSL_IMX8MP_USDHC3,
221 FSL_IMX8MP_VPU,
222 FSL_IMX8MP_VPU_BLK_CTRL,
223 FSL_IMX8MP_VPU_G1_DECODER,
224 FSL_IMX8MP_VPU_G2_DECODER,
225 FSL_IMX8MP_VPU_VC8000E_ENCODER,
226 FSL_IMX8MP_WDOG1,
227 FSL_IMX8MP_WDOG2,
228 FSL_IMX8MP_WDOG3,
229 };
230
231 enum FslImx8mpIrqs {
232 FSL_IMX8MP_USDHC1_IRQ = 22,
233 FSL_IMX8MP_USDHC2_IRQ = 23,
234 FSL_IMX8MP_USDHC3_IRQ = 24,
235
236 FSL_IMX8MP_UART1_IRQ = 26,
237 FSL_IMX8MP_UART2_IRQ = 27,
238 FSL_IMX8MP_UART3_IRQ = 28,
239 FSL_IMX8MP_UART4_IRQ = 29,
240 FSL_IMX8MP_UART5_IRQ = 30,
241 FSL_IMX8MP_UART6_IRQ = 16,
242
243 FSL_IMX8MP_ECSPI1_IRQ = 31,
244 FSL_IMX8MP_ECSPI2_IRQ = 32,
245 FSL_IMX8MP_ECSPI3_IRQ = 33,
246
247 FSL_IMX8MP_I2C1_IRQ = 35,
248 FSL_IMX8MP_I2C2_IRQ = 36,
249 FSL_IMX8MP_I2C3_IRQ = 37,
250 FSL_IMX8MP_I2C4_IRQ = 38,
251
252 FSL_IMX8MP_USB1_IRQ = 40,
253 FSL_IMX8MP_USB2_IRQ = 41,
254
255 FSL_IMX8MP_GPT1_IRQ = 55,
256 FSL_IMX8MP_GPT2_IRQ = 54,
257 FSL_IMX8MP_GPT3_IRQ = 53,
258 FSL_IMX8MP_GPT4_IRQ = 52,
259 FSL_IMX8MP_GPT5_GPT6_IRQ = 51,
260
261 FSL_IMX8MP_GPIO1_LOW_IRQ = 64,
262 FSL_IMX8MP_GPIO1_HIGH_IRQ = 65,
263 FSL_IMX8MP_GPIO2_LOW_IRQ = 66,
264 FSL_IMX8MP_GPIO2_HIGH_IRQ = 67,
265 FSL_IMX8MP_GPIO3_LOW_IRQ = 68,
266 FSL_IMX8MP_GPIO3_HIGH_IRQ = 69,
267 FSL_IMX8MP_GPIO4_LOW_IRQ = 70,
268 FSL_IMX8MP_GPIO4_HIGH_IRQ = 71,
269 FSL_IMX8MP_GPIO5_LOW_IRQ = 72,
270 FSL_IMX8MP_GPIO5_HIGH_IRQ = 73,
271
272 FSL_IMX8MP_I2C5_IRQ = 76,
273 FSL_IMX8MP_I2C6_IRQ = 77,
274
275 FSL_IMX8MP_WDOG1_IRQ = 78,
276 FSL_IMX8MP_WDOG2_IRQ = 79,
277 FSL_IMX8MP_WDOG3_IRQ = 10,
278
279 FSL_IMX8MP_ENET1_MAC_IRQ = 118,
280 FSL_IMX6_ENET1_MAC_1588_IRQ = 121,
281
282 FSL_IMX8MP_PCI_INTA_IRQ = 126,
283 FSL_IMX8MP_PCI_INTB_IRQ = 125,
284 FSL_IMX8MP_PCI_INTC_IRQ = 124,
285 FSL_IMX8MP_PCI_INTD_IRQ = 123,
286 FSL_IMX8MP_PCI_MSI_IRQ = 140,
287
288 FSL_IMX8MP_FLEXCAN1_IRQ = 142,
289 FSL_IMX8MP_FLEXCAN2_IRQ = 144,
290 };
291
292 #endif /* FSL_IMX8MP_H */