| 1 | /* |
| 2 | * Nuvoton NPCM8xx SoC family. |
| 3 | * |
| 4 | * Copyright 2022 Google LLC |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
| 8 | * Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 14 | * for more details. |
| 15 | */ |
| 16 | #ifndef NPCM8XX_H |
| 17 | #define NPCM8XX_H |
| 18 | |
| 19 | #include "hw/adc/npcm7xx_adc.h" |
| 20 | #include "hw/core/split-irq.h" |
| 21 | #include "hw/cpu/cluster.h" |
| 22 | #include "hw/gpio/npcm7xx_gpio.h" |
| 23 | #include "hw/i2c/npcm7xx_smbus.h" |
| 24 | #include "hw/intc/arm_gic_common.h" |
| 25 | #include "hw/mem/npcm7xx_mc.h" |
| 26 | #include "hw/arm/boot.h" |
| 27 | #include "hw/misc/npcm_clk.h" |
| 28 | #include "hw/misc/npcm_gcr.h" |
| 29 | #include "hw/misc/npcm7xx_mft.h" |
| 30 | #include "hw/misc/npcm7xx_pwm.h" |
| 31 | #include "hw/misc/npcm7xx_rng.h" |
| 32 | #include "hw/net/npcm_gmac.h" |
| 33 | #include "hw/net/npcm_pcs.h" |
| 34 | #include "hw/nvram/npcm7xx_otp.h" |
| 35 | #include "hw/sd/npcm7xx_sdhci.h" |
| 36 | #include "hw/timer/npcm7xx_timer.h" |
| 37 | #include "hw/ssi/npcm7xx_fiu.h" |
| 38 | #include "hw/usb/hcd-ehci.h" |
| 39 | #include "hw/usb/hcd-ohci.h" |
| 40 | #include "target/arm/cpu.h" |
| 41 | #include "hw/ssi/npcm_pspi.h" |
| 42 | |
| 43 | #define NPCM8XX_MAX_NUM_CPUS (4) |
| 44 | |
| 45 | /* The first half of the address space is reserved for DDR4 DRAM. */ |
| 46 | #define NPCM8XX_DRAM_BA (0x00000000) |
| 47 | #define NPCM8XX_DRAM_SZ (2 * GiB) |
| 48 | |
| 49 | /* Magic addresses for setting up direct kernel booting and SMP boot stubs. */ |
| 50 | #define NPCM8XX_LOADER_START (0x00000000) /* Start of SDRAM */ |
| 51 | #define NPCM8XX_SMP_LOADER_START (0xffff0000) /* Boot ROM */ |
| 52 | #define NPCM8XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ |
| 53 | #define NPCM8XX_BOARD_SETUP_ADDR (0xffff1000) /* Boot ROM */ |
| 54 | |
| 55 | #define NPCM8XX_NR_PWM_MODULES 3 |
| 56 | |
| 57 | struct NPCM8xxMachine { |
| 58 | MachineState parent_obj; |
| 59 | |
| 60 | /* |
| 61 | * PWM fan splitter. each splitter connects to one PWM output and |
| 62 | * multiple MFT inputs. |
| 63 | */ |
| 64 | SplitIRQ fan_splitter[NPCM8XX_NR_PWM_MODULES * |
| 65 | NPCM7XX_PWM_PER_MODULE]; |
| 66 | struct arm_boot_info bootinfo; |
| 67 | }; |
| 68 | |
| 69 | |
| 70 | struct NPCM8xxMachineClass { |
| 71 | MachineClass parent_class; |
| 72 | |
| 73 | const char *soc_type; |
| 74 | }; |
| 75 | |
| 76 | #define TYPE_NPCM8XX_MACHINE MACHINE_TYPE_NAME("npcm8xx") |
| 77 | OBJECT_DECLARE_TYPE(NPCM8xxMachine, NPCM8xxMachineClass, NPCM8XX_MACHINE) |
| 78 | |
| 79 | struct NPCM8xxState { |
| 80 | DeviceState parent_obj; |
| 81 | |
| 82 | ARMCPU cpu[NPCM8XX_MAX_NUM_CPUS]; |
| 83 | CPUClusterState cpu_cluster; |
| 84 | GICState gic; |
| 85 | |
| 86 | MemoryRegion sram; |
| 87 | MemoryRegion irom; |
| 88 | MemoryRegion ram3; |
| 89 | MemoryRegion *dram; |
| 90 | |
| 91 | NPCMGCRState gcr; |
| 92 | NPCMCLKState clk; |
| 93 | NPCM7xxTimerCtrlState tim[3]; |
| 94 | NPCM7xxADCState adc; |
| 95 | NPCM7xxPWMState pwm[NPCM8XX_NR_PWM_MODULES]; |
| 96 | NPCM7xxMFTState mft[8]; |
| 97 | NPCM7xxOTPState fuse_array; |
| 98 | NPCM7xxMCState mc; |
| 99 | NPCM7xxRNGState rng; |
| 100 | NPCM7xxGPIOState gpio[8]; |
| 101 | NPCM7xxSMBusState smbus[27]; |
| 102 | EHCISysBusState ehci[2]; |
| 103 | OHCISysBusState ohci[2]; |
| 104 | NPCM7xxFIUState fiu[3]; |
| 105 | NPCMGMACState gmac[4]; |
| 106 | NPCMPCSState pcs; |
| 107 | NPCM7xxSDHCIState mmc; |
| 108 | NPCMPSPIState pspi; |
| 109 | }; |
| 110 | |
| 111 | struct NPCM8xxClass { |
| 112 | DeviceClass parent_class; |
| 113 | |
| 114 | /* Bitmask of modules that are permanently disabled on this chip. */ |
| 115 | uint32_t disabled_modules; |
| 116 | /* Number of CPU cores enabled in this SoC class. */ |
| 117 | uint32_t num_cpus; |
| 118 | }; |
| 119 | |
| 120 | #define TYPE_NPCM8XX "npcm8xx" |
| 121 | OBJECT_DECLARE_TYPE(NPCM8xxState, NPCM8xxClass, NPCM8XX) |
| 122 | |
| 123 | /** |
| 124 | * npcm8xx_load_kernel - Loads memory with everything needed to boot |
| 125 | * @machine - The machine containing the SoC to be booted. |
| 126 | * @soc - The SoC containing the CPU to be booted. |
| 127 | * @binfo - Caller owned boot info structure to be filled in. |
| 128 | * |
| 129 | * This will set up the ARM boot info structure for the specific NPCM8xx |
| 130 | * derivative and call arm_load_kernel() to set up loading of the kernel, etc. |
| 131 | * into memory, if requested by the user. The boot info is owned by the |
| 132 | * caller because arm_load_kernel() keeps a pointer to it for the lifetime |
| 133 | * of the CPUs. |
| 134 | */ |
| 135 | void npcm8xx_load_kernel(MachineState *machine, NPCM8xxState *soc, |
| 136 | struct arm_boot_info *binfo); |
| 137 | |
| 138 | #endif /* NPCM8XX_H */ |