| 1 | /* |
| 2 | * Texas Instruments OMAP processors. |
| 3 | * |
| 4 | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 or |
| 9 | * (at your option) version 3 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef HW_ARM_OMAP_H |
| 21 | #define HW_ARM_OMAP_H |
| 22 | |
| 23 | #include "system/memory.h" |
| 24 | #include "target/arm/cpu-qom.h" |
| 25 | #include "qemu/log.h" |
| 26 | #include "qom/object.h" |
| 27 | |
| 28 | #define OMAP_EMIFS_BASE 0x00000000 |
| 29 | #define OMAP_CS0_BASE 0x00000000 |
| 30 | #define OMAP_CS1_BASE 0x04000000 |
| 31 | #define OMAP_CS2_BASE 0x08000000 |
| 32 | #define OMAP_CS3_BASE 0x0c000000 |
| 33 | #define OMAP_EMIFF_BASE 0x10000000 |
| 34 | #define OMAP_IMIF_BASE 0x20000000 |
| 35 | #define OMAP_LOCALBUS_BASE 0x30000000 |
| 36 | #define OMAP_MPUI_BASE 0xe1000000 |
| 37 | |
| 38 | #define OMAP15XX_SRAM_SIZE 0x00030000 |
| 39 | #define OMAP_CS0_SIZE 0x04000000 |
| 40 | #define OMAP_CS1_SIZE 0x04000000 |
| 41 | #define OMAP_CS2_SIZE 0x04000000 |
| 42 | #define OMAP_CS3_SIZE 0x04000000 |
| 43 | |
| 44 | /* omap_clk.c */ |
| 45 | struct omap_mpu_state_s; |
| 46 | typedef struct clk *omap_clk; |
| 47 | omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
| 48 | void omap_clk_init(struct omap_mpu_state_s *mpu); |
| 49 | void omap_clk_adduser(struct clk *clk, qemu_irq user); |
| 50 | void omap_clk_get(omap_clk clk); |
| 51 | void omap_clk_put(omap_clk clk); |
| 52 | void omap_clk_onoff(omap_clk clk, int on); |
| 53 | void omap_clk_canidle(omap_clk clk, int can); |
| 54 | void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
| 55 | int64_t omap_clk_getrate(omap_clk clk); |
| 56 | void omap_clk_reparent(omap_clk clk, omap_clk parent); |
| 57 | |
| 58 | /* omap_intc.c */ |
| 59 | #define TYPE_OMAP_INTC "omap-intc" |
| 60 | typedef struct OMAPIntcState OMAPIntcState; |
| 61 | DECLARE_INSTANCE_CHECKER(OMAPIntcState, OMAP_INTC, TYPE_OMAP_INTC) |
| 62 | |
| 63 | |
| 64 | /* |
| 65 | * TODO: Ideally we should have a clock framework that |
| 66 | * let us wire these clocks up with QOM properties or links. |
| 67 | * |
| 68 | * qdev should support a generic means of defining a 'port' with |
| 69 | * an arbitrary interface for connecting two devices. Then we |
| 70 | * could reframe the omap clock API in terms of clock ports, |
| 71 | * and get some type safety. For now the best qdev provides is |
| 72 | * passing an arbitrary pointer. |
| 73 | * (It's not possible to pass in the string which is the clock |
| 74 | * name, because this device does not have the necessary information |
| 75 | * (ie the struct omap_mpu_state_s*) to do the clockname to pointer |
| 76 | * translation.) |
| 77 | */ |
| 78 | void omap_intc_set_iclk(OMAPIntcState *intc, omap_clk clk); |
| 79 | void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk); |
| 80 | |
| 81 | /* omap_i2c.c */ |
| 82 | #define TYPE_OMAP_I2C "omap_i2c" |
| 83 | OBJECT_DECLARE_SIMPLE_TYPE(OMAPI2CState, OMAP_I2C) |
| 84 | |
| 85 | |
| 86 | /* TODO: clock framework (see above) */ |
| 87 | void omap_i2c_set_iclk(OMAPI2CState *i2c, omap_clk clk); |
| 88 | void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk); |
| 89 | |
| 90 | /* omap_gpio.c */ |
| 91 | #define TYPE_OMAP1_GPIO "omap-gpio" |
| 92 | typedef struct Omap1GpioState Omap1GpioState; |
| 93 | DECLARE_INSTANCE_CHECKER(Omap1GpioState, OMAP1_GPIO, |
| 94 | TYPE_OMAP1_GPIO) |
| 95 | |
| 96 | /* TODO: clock framework (see above) */ |
| 97 | void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk); |
| 98 | |
| 99 | /* |
| 100 | * Common IRQ numbers for level 1 interrupt handler |
| 101 | * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. |
| 102 | */ |
| 103 | #define OMAP_INT_CAMERA 1 |
| 104 | #define OMAP_INT_FIQ 3 |
| 105 | #define OMAP_INT_RTDX 6 |
| 106 | #define OMAP_INT_DSP_MMU_ABORT 7 |
| 107 | #define OMAP_INT_HOST 8 |
| 108 | #define OMAP_INT_ABORT 9 |
| 109 | #define OMAP_INT_BRIDGE_PRIV 13 |
| 110 | #define OMAP_INT_GPIO_BANK1 14 |
| 111 | #define OMAP_INT_UART3 15 |
| 112 | #define OMAP_INT_TIMER3 16 |
| 113 | #define OMAP_INT_DMA_CH0_6 19 |
| 114 | #define OMAP_INT_DMA_CH1_7 20 |
| 115 | #define OMAP_INT_DMA_CH2_8 21 |
| 116 | #define OMAP_INT_DMA_CH3 22 |
| 117 | #define OMAP_INT_DMA_CH4 23 |
| 118 | #define OMAP_INT_DMA_CH5 24 |
| 119 | #define OMAP_INT_DMA_LCD 25 |
| 120 | #define OMAP_INT_TIMER1 26 |
| 121 | #define OMAP_INT_WD_TIMER 27 |
| 122 | #define OMAP_INT_BRIDGE_PUB 28 |
| 123 | #define OMAP_INT_TIMER2 30 |
| 124 | #define OMAP_INT_LCD_CTRL 31 |
| 125 | |
| 126 | /* |
| 127 | * Common OMAP-15xx IRQ numbers for level 1 interrupt handler |
| 128 | */ |
| 129 | #define OMAP_INT_15XX_IH2_IRQ 0 |
| 130 | |
| 131 | /* |
| 132 | * OMAP-310 specific IRQ numbers for level 1 interrupt handler |
| 133 | */ |
| 134 | #define OMAP_INT_310_McBSP2_TX 4 |
| 135 | #define OMAP_INT_310_McBSP2_RX 5 |
| 136 | #define OMAP_INT_310_HSB_MAILBOX1 12 |
| 137 | #define OMAP_INT_310_HSAB_MMU 18 |
| 138 | |
| 139 | /* |
| 140 | * Common IRQ numbers for level 2 interrupt handler |
| 141 | */ |
| 142 | #define OMAP_INT_KEYBOARD 1 |
| 143 | #define OMAP_INT_uWireTX 2 |
| 144 | #define OMAP_INT_uWireRX 3 |
| 145 | #define OMAP_INT_I2C 4 |
| 146 | #define OMAP_INT_MPUIO 5 |
| 147 | #define OMAP_INT_USB_HHC_1 6 |
| 148 | #define OMAP_INT_McBSP3TX 10 |
| 149 | #define OMAP_INT_McBSP3RX 11 |
| 150 | #define OMAP_INT_McBSP1TX 12 |
| 151 | #define OMAP_INT_McBSP1RX 13 |
| 152 | #define OMAP_INT_UART1 14 |
| 153 | #define OMAP_INT_UART2 15 |
| 154 | #define OMAP_INT_USB_W2FC 20 |
| 155 | #define OMAP_INT_1WIRE 21 |
| 156 | #define OMAP_INT_OS_TIMER 22 |
| 157 | #define OMAP_INT_OQN 23 |
| 158 | #define OMAP_INT_GAUGE_32K 24 |
| 159 | #define OMAP_INT_RTC_TIMER 25 |
| 160 | #define OMAP_INT_RTC_ALARM 26 |
| 161 | #define OMAP_INT_DSP_MMU 28 |
| 162 | |
| 163 | /* |
| 164 | * OMAP-310 specific IRQ numbers for level 2 interrupt handler |
| 165 | */ |
| 166 | #define OMAP_INT_310_FAC 0 |
| 167 | #define OMAP_INT_310_USB_HHC_2 7 |
| 168 | #define OMAP_INT_310_MCSI1_FE 16 |
| 169 | #define OMAP_INT_310_MCSI2_FE 17 |
| 170 | #define OMAP_INT_310_USB_W2FC_ISO 29 |
| 171 | #define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
| 172 | #define OMAP_INT_310_McBSP2RX_OF 31 |
| 173 | |
| 174 | /* omap_dma.c */ |
| 175 | struct soc_dma_s; |
| 176 | struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, |
| 177 | MemoryRegion *sysmem, |
| 178 | qemu_irq lcd_irq, |
| 179 | struct omap_mpu_state_s *mpu, omap_clk clk); |
| 180 | void omap_dma_reset(struct soc_dma_s *s); |
| 181 | |
| 182 | struct dma_irq_map { |
| 183 | int ih; |
| 184 | int intr; |
| 185 | }; |
| 186 | |
| 187 | /* Only used in OMAP DMA 3.x gigacells */ |
| 188 | enum omap_dma_port { |
| 189 | emiff = 0, |
| 190 | emifs, |
| 191 | imif, /* omap16xx: ocp_t1 */ |
| 192 | tipb, |
| 193 | local, /* omap16xx: ocp_t2 */ |
| 194 | tipb_mpui, |
| 195 | __omap_dma_port_last, |
| 196 | }; |
| 197 | |
| 198 | typedef enum { |
| 199 | constant = 0, |
| 200 | post_incremented, |
| 201 | single_index, |
| 202 | double_index, |
| 203 | } omap_dma_addressing_t; |
| 204 | |
| 205 | /* Only used in OMAP DMA 3.x gigacells */ |
| 206 | struct omap_dma_lcd_channel_s { |
| 207 | enum omap_dma_port src; |
| 208 | hwaddr src_f1_top; |
| 209 | hwaddr src_f1_bottom; |
| 210 | hwaddr src_f2_top; |
| 211 | hwaddr src_f2_bottom; |
| 212 | |
| 213 | /* Destination port is fixed. */ |
| 214 | int interrupts; |
| 215 | int condition; |
| 216 | int dual; |
| 217 | |
| 218 | int current_frame; |
| 219 | hwaddr phys_framebuffer[2]; |
| 220 | qemu_irq irq; |
| 221 | struct omap_mpu_state_s *mpu; |
| 222 | } *omap_dma_get_lcdch(struct soc_dma_s *s); |
| 223 | |
| 224 | /* |
| 225 | * DMA request numbers for OMAP1 |
| 226 | * See /usr/include/asm-arm/arch-omap/dma.h in Linux. |
| 227 | */ |
| 228 | #define OMAP_DMA_NO_DEVICE 0 |
| 229 | #define OMAP_DMA_MCSI1_TX 1 |
| 230 | #define OMAP_DMA_MCSI1_RX 2 |
| 231 | #define OMAP_DMA_I2C_RX 3 |
| 232 | #define OMAP_DMA_I2C_TX 4 |
| 233 | #define OMAP_DMA_EXT_NDMA_REQ0 5 |
| 234 | #define OMAP_DMA_EXT_NDMA_REQ1 6 |
| 235 | #define OMAP_DMA_UWIRE_TX 7 |
| 236 | #define OMAP_DMA_MCBSP1_TX 8 |
| 237 | #define OMAP_DMA_MCBSP1_RX 9 |
| 238 | #define OMAP_DMA_MCBSP3_TX 10 |
| 239 | #define OMAP_DMA_MCBSP3_RX 11 |
| 240 | #define OMAP_DMA_UART1_TX 12 |
| 241 | #define OMAP_DMA_UART1_RX 13 |
| 242 | #define OMAP_DMA_UART2_TX 14 |
| 243 | #define OMAP_DMA_UART2_RX 15 |
| 244 | #define OMAP_DMA_MCBSP2_TX 16 |
| 245 | #define OMAP_DMA_MCBSP2_RX 17 |
| 246 | #define OMAP_DMA_UART3_TX 18 |
| 247 | #define OMAP_DMA_UART3_RX 19 |
| 248 | #define OMAP_DMA_CAMERA_IF_RX 20 |
| 249 | #define OMAP_DMA_MMC_TX 21 |
| 250 | #define OMAP_DMA_MMC_RX 22 |
| 251 | #define OMAP_DMA_USB_W2FC_RX0 26 |
| 252 | #define OMAP_DMA_USB_W2FC_RX1 27 |
| 253 | #define OMAP_DMA_USB_W2FC_RX2 28 |
| 254 | #define OMAP_DMA_USB_W2FC_TX0 29 |
| 255 | #define OMAP_DMA_USB_W2FC_TX1 30 |
| 256 | #define OMAP_DMA_USB_W2FC_TX2 31 |
| 257 | |
| 258 | struct omap_uart_s; |
| 259 | struct omap_uart_s *omap_uart_init(hwaddr base, |
| 260 | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
| 261 | qemu_irq txdma, qemu_irq rxdma, |
| 262 | const char *label, Chardev *chr); |
| 263 | void omap_uart_reset(struct omap_uart_s *s); |
| 264 | |
| 265 | struct omap_mpuio_s; |
| 266 | |
| 267 | struct omap_uwire_s; |
| 268 | |
| 269 | struct I2SCodec { |
| 270 | void *opaque; |
| 271 | |
| 272 | /* The CPU can call this if it is generating the clock signal on the |
| 273 | * i2s port. The CODEC can ignore it if it is set up as a clock |
| 274 | * master and generates its own clock. */ |
| 275 | void (*set_rate)(void *opaque, int in, int out); |
| 276 | |
| 277 | void (*tx_swallow)(void *opaque); |
| 278 | qemu_irq rx_swallow; |
| 279 | qemu_irq tx_start; |
| 280 | |
| 281 | int tx_rate; |
| 282 | int cts; |
| 283 | int rx_rate; |
| 284 | int rts; |
| 285 | |
| 286 | struct i2s_fifo_s { |
| 287 | uint8_t *fifo; |
| 288 | int len; |
| 289 | int start; |
| 290 | int size; |
| 291 | } in, out; |
| 292 | }; |
| 293 | struct omap_mcbsp_s; |
| 294 | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); |
| 295 | |
| 296 | /* omap_lcdc.c */ |
| 297 | struct omap_lcd_panel_s; |
| 298 | void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
| 299 | struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, |
| 300 | hwaddr base, |
| 301 | qemu_irq irq, |
| 302 | struct omap_dma_lcd_channel_s *dma, |
| 303 | omap_clk clk); |
| 304 | |
| 305 | /* omap_mmc.c */ |
| 306 | #define TYPE_OMAP_MMC "omap-mmc" |
| 307 | OBJECT_DECLARE_SIMPLE_TYPE(OMAPMMCState, OMAP_MMC) |
| 308 | |
| 309 | DeviceState *omap_mmc_init(hwaddr base, |
| 310 | MemoryRegion *sysmem, |
| 311 | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
| 312 | /* TODO: clock framework (see above) */ |
| 313 | void omap_mmc_set_clk(DeviceState *dev, omap_clk clk); |
| 314 | |
| 315 | |
| 316 | /* omap_i2c.c */ |
| 317 | I2CBus *omap_i2c_bus(DeviceState *omap_i2c); |
| 318 | |
| 319 | struct omap_mpu_state_s { |
| 320 | ARMCPU *cpu; |
| 321 | |
| 322 | qemu_irq *drq; |
| 323 | |
| 324 | qemu_irq wakeup; |
| 325 | |
| 326 | MemoryRegion ulpd_pm_iomem; |
| 327 | MemoryRegion pin_cfg_iomem; |
| 328 | MemoryRegion id_iomem; |
| 329 | MemoryRegion id_iomem_e18; |
| 330 | MemoryRegion id_iomem_ed4; |
| 331 | MemoryRegion mpui_iomem; |
| 332 | MemoryRegion tcmi_iomem; |
| 333 | MemoryRegion clkm_iomem; |
| 334 | MemoryRegion clkdsp_iomem; |
| 335 | MemoryRegion mpui_io_iomem; |
| 336 | MemoryRegion tap_iomem; |
| 337 | MemoryRegion imif_ram; |
| 338 | MemoryRegion sram; |
| 339 | |
| 340 | struct omap_dma_port_if_s { |
| 341 | uint32_t (*read[3])(struct omap_mpu_state_s *s, |
| 342 | hwaddr offset); |
| 343 | void (*write[3])(struct omap_mpu_state_s *s, |
| 344 | hwaddr offset, uint32_t value); |
| 345 | int (*addr_valid)(struct omap_mpu_state_s *s, |
| 346 | hwaddr addr); |
| 347 | } port[__omap_dma_port_last]; |
| 348 | |
| 349 | uint64_t sdram_size; |
| 350 | unsigned long sram_size; |
| 351 | |
| 352 | /* MPUI-TIPB peripherals */ |
| 353 | struct omap_uart_s *uart[3]; |
| 354 | |
| 355 | DeviceState *gpio; |
| 356 | |
| 357 | struct omap_mcbsp_s *mcbsp1; |
| 358 | struct omap_mcbsp_s *mcbsp3; |
| 359 | |
| 360 | /* MPU public TIPB peripherals */ |
| 361 | struct omap_32khz_timer_s *os_timer; |
| 362 | |
| 363 | DeviceState *mmc; |
| 364 | |
| 365 | struct omap_mpuio_s *mpuio; |
| 366 | |
| 367 | struct omap_uwire_s *microwire; |
| 368 | |
| 369 | struct omap_pwl_s *pwl; |
| 370 | struct omap_pwt_s *pwt; |
| 371 | DeviceState *i2c[2]; |
| 372 | |
| 373 | struct omap_rtc_s *rtc; |
| 374 | |
| 375 | struct omap_mcbsp_s *mcbsp2; |
| 376 | |
| 377 | struct omap_lpg_s *led[2]; |
| 378 | |
| 379 | /* MPU private TIPB peripherals */ |
| 380 | DeviceState *ih[2]; |
| 381 | |
| 382 | struct soc_dma_s *dma; |
| 383 | |
| 384 | struct omap_mpu_timer_s *timer[3]; |
| 385 | struct omap_watchdog_timer_s *wdt; |
| 386 | |
| 387 | struct omap_lcd_panel_s *lcd; |
| 388 | |
| 389 | uint32_t ulpd_pm_regs[21]; |
| 390 | int64_t ulpd_gauge_start; |
| 391 | |
| 392 | uint32_t func_mux_ctrl[14]; |
| 393 | uint32_t comp_mode_ctrl[1]; |
| 394 | uint32_t pull_dwn_ctrl[4]; |
| 395 | uint32_t gate_inh_ctrl[1]; |
| 396 | uint32_t voltage_ctrl[1]; |
| 397 | uint32_t test_dbg_ctrl[1]; |
| 398 | uint32_t mod_conf_ctrl[1]; |
| 399 | int compat1509; |
| 400 | |
| 401 | uint32_t mpui_ctrl; |
| 402 | |
| 403 | struct omap_tipb_bridge_s *private_tipb; |
| 404 | struct omap_tipb_bridge_s *public_tipb; |
| 405 | |
| 406 | uint32_t tcmi_regs[17]; |
| 407 | |
| 408 | struct dpll_ctl_s *dpll[3]; |
| 409 | |
| 410 | omap_clk clks; |
| 411 | struct { |
| 412 | int cold_start; |
| 413 | int clocking_scheme; |
| 414 | uint16_t arm_ckctl; |
| 415 | uint16_t arm_idlect1; |
| 416 | uint16_t arm_idlect2; |
| 417 | uint16_t arm_ewupct; |
| 418 | uint16_t arm_rstct1; |
| 419 | uint16_t arm_rstct2; |
| 420 | uint16_t arm_ckout1; |
| 421 | int dpll1_mode; |
| 422 | uint16_t dsp_idlect1; |
| 423 | uint16_t dsp_idlect2; |
| 424 | uint16_t dsp_rstct2; |
| 425 | } clkm; |
| 426 | }; |
| 427 | |
| 428 | /* omap1.c */ |
| 429 | struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *sdram, |
| 430 | const char *core); |
| 431 | |
| 432 | #define OMAP_BAD_REG(paddr) \ |
| 433 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ |
| 434 | __func__, paddr) |
| 435 | #define OMAP_RO_REG(paddr) \ |
| 436 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ |
| 437 | HWADDR_PRIx "\n", \ |
| 438 | __func__, paddr) |
| 439 | |
| 440 | #define OMAP_MPUI_REG_MASK 0x000007ff |
| 441 | |
| 442 | #endif |