| 1 | /* |
| 2 | * Copyright (C) 2014-2016 Broadcom Corporation |
| 3 | * Copyright (c) 2017 Red Hat, Inc. |
| 4 | * Written by Prem Mallappa, Eric Auger |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along |
| 16 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef HW_ARM_SMMUV3_H |
| 20 | #define HW_ARM_SMMUV3_H |
| 21 | |
| 22 | #include "hw/arm/smmu-common.h" |
| 23 | #include "qom/object.h" |
| 24 | #include "qapi/qapi-types-misc-arm.h" |
| 25 | #include "qemu/notify.h" |
| 26 | |
| 27 | #define TYPE_SMMUV3_IOMMU_MEMORY_REGION "smmuv3-iommu-memory-region" |
| 28 | |
| 29 | typedef struct SMMUQueue { |
| 30 | uint64_t base; /* base register */ |
| 31 | uint32_t prod; |
| 32 | uint32_t cons; |
| 33 | uint8_t entry_size; |
| 34 | uint8_t log2size; |
| 35 | } SMMUQueue; |
| 36 | |
| 37 | struct SMMUv3State { |
| 38 | SMMUState smmu_state; |
| 39 | |
| 40 | uint32_t features; |
| 41 | uint8_t sid_size; |
| 42 | uint8_t sid_split; |
| 43 | |
| 44 | uint32_t idr[6]; |
| 45 | uint32_t iidr; |
| 46 | uint32_t aidr; |
| 47 | uint32_t cr[3]; |
| 48 | uint32_t cr0ack; |
| 49 | uint32_t statusr; |
| 50 | uint32_t gbpa; |
| 51 | uint32_t irq_ctrl; |
| 52 | uint32_t gerror; |
| 53 | uint32_t gerrorn; |
| 54 | uint64_t gerror_irq_cfg0; |
| 55 | uint32_t gerror_irq_cfg1; |
| 56 | uint32_t gerror_irq_cfg2; |
| 57 | uint64_t strtab_base; |
| 58 | uint32_t strtab_base_cfg; |
| 59 | uint64_t eventq_irq_cfg0; |
| 60 | uint32_t eventq_irq_cfg1; |
| 61 | uint32_t eventq_irq_cfg2; |
| 62 | |
| 63 | SMMUQueue eventq, cmdq; |
| 64 | |
| 65 | qemu_irq irq[4]; |
| 66 | QemuMutex mutex; |
| 67 | char *stage; |
| 68 | uint8_t identifier; |
| 69 | |
| 70 | /* SMMU has HW accelerator support for nested S1 + s2 */ |
| 71 | bool accel; |
| 72 | struct SMMUv3AccelState *s_accel; |
| 73 | uint64_t msi_gpa; |
| 74 | Error *migration_blocker; |
| 75 | OnOffAuto ril; |
| 76 | OnOffAuto ats; |
| 77 | OasMode oas; |
| 78 | SsidSizeMode ssidsize; |
| 79 | /* SMMU CMDQV extension */ |
| 80 | OnOffAuto cmdqv; |
| 81 | |
| 82 | Notifier machine_done; |
| 83 | }; |
| 84 | |
| 85 | typedef enum { |
| 86 | SMMU_IRQ_EVTQ, |
| 87 | SMMU_IRQ_PRIQ, |
| 88 | SMMU_IRQ_CMD_SYNC, |
| 89 | SMMU_IRQ_GERROR, |
| 90 | } SMMUIrq; |
| 91 | |
| 92 | struct SMMUv3Class { |
| 93 | /*< private >*/ |
| 94 | SMMUBaseClass smmu_base_class; |
| 95 | /*< public >*/ |
| 96 | |
| 97 | DeviceRealize parent_realize; |
| 98 | ResettablePhases parent_phases; |
| 99 | }; |
| 100 | |
| 101 | bool smmuv3_ats_enabled(struct SMMUv3State *s); |
| 102 | |
| 103 | #define TYPE_ARM_SMMUV3 "arm-smmuv3" |
| 104 | OBJECT_DECLARE_TYPE(SMMUv3State, SMMUv3Class, ARM_SMMUV3) |
| 105 | |
| 106 | #define STAGE1_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S1P) |
| 107 | #define STAGE2_SUPPORTED(s) FIELD_EX32(s->idr[0], IDR0, S2P) |
| 108 | |
| 109 | #endif |