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1 /*
2 * Xilinx Zynq MPSoC emulation
3 *
4 * Copyright (C) 2015 Xilinx Inc
5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 * for more details.
16 */
17
18 #ifndef XLNX_ZYNQMP_H
19 #define XLNX_ZYNQMP_H
20
21 #include "hw/intc/arm_gic.h"
22 #include "hw/net/cadence_gem.h"
23 #include "hw/char/cadence_uart.h"
24 #include "hw/net/xlnx-zynqmp-can.h"
25 #include "hw/ide/ahci-sysbus.h"
26 #include "hw/sd/sdhci.h"
27 #include "hw/ssi/xilinx_spips.h"
28 #include "hw/dma/xlnx_dpdma.h"
29 #include "hw/dma/xlnx-zdma.h"
30 #include "hw/display/xlnx_dp.h"
31 #include "hw/intc/xlnx-zynqmp-ipi.h"
32 #include "hw/rtc/xlnx-zynqmp-rtc.h"
33 #include "hw/cpu/cluster.h"
34 #include "target/arm/cpu.h"
35 #include "qom/object.h"
36 #include "net/can_emu.h"
37 #include "hw/dma/xlnx_csu_dma.h"
38 #include "hw/nvram/xlnx-bbram.h"
39 #include "hw/nvram/xlnx-zynqmp-efuse.h"
40 #include "hw/core/or-irq.h"
41 #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
42 #include "hw/misc/xlnx-zynqmp-crf.h"
43 #include "hw/timer/cadence_ttc.h"
44 #include "hw/usb/hcd-dwc3.h"
45 #include "hw/core/split-irq.h"
46
47 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
48 OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
49
50 #define XLNX_ZYNQMP_NUM_APU_CPUS 4
51 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2
52 #define XLNX_ZYNQMP_NUM_GEMS 4
53 #define XLNX_ZYNQMP_NUM_UARTS 2
54 #define XLNX_ZYNQMP_NUM_CAN 2
55 #define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
56 #define XLNX_ZYNQMP_NUM_SDHCI 2
57 #define XLNX_ZYNQMP_NUM_SPIS 2
58 #define XLNX_ZYNQMP_NUM_GDMA_CH 8
59 #define XLNX_ZYNQMP_NUM_ADMA_CH 8
60 #define XLNX_ZYNQMP_NUM_USB 2
61
62 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2
63 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
64 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4
65
66 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
67 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
68 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
69
70 #define XLNX_ZYNQMP_GIC_REGIONS 6
71 #define XLNX_ZYNQMP_GIC_NUM_SPI_INTR 160
72
73 /*
74 * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
75 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
76 * aligned address in the 64k region. To implement each GIC region needs a
77 * number of memory region aliases.
78 */
79
80 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
81 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
82
83 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
84
85 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull
86 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull
87
88 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
89 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
90
91 #define XLNX_ZYNQMP_NUM_TTC 4
92
93 /*
94 * Unimplemented mmio regions needed to boot some images.
95 */
96 #define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
97
98 struct XlnxZynqMPState {
99 /*< private >*/
100 DeviceState parent_obj;
101
102 /*< public >*/
103 CPUClusterState apu_cluster;
104 CPUClusterState rpu_cluster;
105 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
106 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
107 GICState gic;
108 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
109
110 GICState rpu_gic;
111 SplitIRQ splitter[XLNX_ZYNQMP_GIC_NUM_SPI_INTR];
112
113 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
114
115 MemoryRegion *ddr_ram;
116 MemoryRegion ddr_ram_low, ddr_ram_high;
117 XlnxBBRam bbram;
118 XlnxEFuse efuse;
119 XlnxZynqMPEFuse efuse_ctrl;
120
121 MemoryRegion mr_unimp[XLNX_ZYNQMP_NUM_UNIMP_AREAS];
122
123 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
124 OrIRQState gem_irq_orgate[XLNX_ZYNQMP_NUM_GEMS];
125 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
126 XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
127 SysbusAHCIState sata;
128 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
129 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
130 XlnxZynqMPQSPIPS qspi;
131 XlnxDPState dp;
132 XlnxDPDMAState dpdma;
133 XlnxZynqMPIPI ipi;
134 XlnxZynqMPRTC rtc;
135 XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH];
136 XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
137 XlnxCSUDMA qspi_dma;
138 OrIRQState qspi_irq_orgate;
139 XlnxZynqMPAPUCtrl apu_ctrl;
140 XlnxZynqMPCRF crf;
141 CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
142 USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
143
144 char *boot_cpu;
145 ARMCPU *boot_cpu_ptr;
146
147 /* Has the ARM Security extensions? */
148 bool secure;
149 /* Has the ARM Virtualization extensions? */
150 bool virt;
151
152 /* CAN bus. */
153 CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
154 };
155
156 #endif