| 1 | /* |
| 2 | * SiFive UART interface |
| 3 | * |
| 4 | * Copyright (c) 2016 Stefan O'Rear |
| 5 | * Copyright (c) 2017 SiFive, Inc. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms and conditions of the GNU General Public License, |
| 9 | * version 2 or later, as published by the Free Software Foundation. |
| 10 | * |
| 11 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 14 | * more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along with |
| 17 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef HW_SIFIVE_UART_H |
| 21 | #define HW_SIFIVE_UART_H |
| 22 | |
| 23 | #include "chardev/char-fe.h" |
| 24 | #include "hw/core/qdev-properties.h" |
| 25 | #include "hw/core/sysbus.h" |
| 26 | #include "qom/object.h" |
| 27 | #include "qemu/fifo8.h" |
| 28 | |
| 29 | enum { |
| 30 | SIFIVE_UART_TXFIFO = 0, |
| 31 | SIFIVE_UART_RXFIFO = 4, |
| 32 | SIFIVE_UART_TXCTRL = 8, |
| 33 | SIFIVE_UART_TXMARK = 10, |
| 34 | SIFIVE_UART_RXCTRL = 12, |
| 35 | SIFIVE_UART_RXMARK = 14, |
| 36 | SIFIVE_UART_IE = 16, |
| 37 | SIFIVE_UART_IP = 20, |
| 38 | SIFIVE_UART_DIV = 24, |
| 39 | SIFIVE_UART_MAX = 32 |
| 40 | }; |
| 41 | |
| 42 | enum { |
| 43 | SIFIVE_UART_IE_TXWM = 1, /* Transmit watermark interrupt enable */ |
| 44 | SIFIVE_UART_IE_RXWM = 2 /* Receive watermark interrupt enable */ |
| 45 | }; |
| 46 | |
| 47 | enum { |
| 48 | SIFIVE_UART_IP_TXWM = 1, /* Transmit watermark interrupt pending */ |
| 49 | SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ |
| 50 | }; |
| 51 | |
| 52 | #define SIFIVE_UART_TXFIFO_FULL 0x80000000 |
| 53 | |
| 54 | #define SIFIVE_UART_TXEN(txctrl) (txctrl & 0x1) |
| 55 | #define SIFIVE_UART_RXEN(rxctrl) (rxctrl & 0x1) |
| 56 | #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) |
| 57 | #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) |
| 58 | |
| 59 | #define SIFIVE_UART_RX_FIFO_SIZE 8 |
| 60 | #define SIFIVE_UART_TX_FIFO_SIZE 8 |
| 61 | |
| 62 | #define TYPE_SIFIVE_UART "riscv.sifive.uart" |
| 63 | OBJECT_DECLARE_SIMPLE_TYPE(SiFiveUARTState, SIFIVE_UART) |
| 64 | |
| 65 | struct SiFiveUARTState { |
| 66 | /*< private >*/ |
| 67 | SysBusDevice parent_obj; |
| 68 | |
| 69 | /*< public >*/ |
| 70 | qemu_irq irq; |
| 71 | MemoryRegion mmio; |
| 72 | CharFrontend chr; |
| 73 | |
| 74 | uint32_t txfifo; |
| 75 | uint32_t ie; |
| 76 | uint32_t txctrl; |
| 77 | uint32_t rxctrl; |
| 78 | uint32_t div; |
| 79 | |
| 80 | uint8_t rx_fifo[SIFIVE_UART_RX_FIFO_SIZE]; |
| 81 | uint8_t rx_fifo_len; |
| 82 | |
| 83 | Fifo8 tx_fifo; |
| 84 | |
| 85 | QEMUTimer *fifo_trigger_handle; |
| 86 | }; |
| 87 | |
| 88 | SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base, |
| 89 | Chardev *chr, qemu_irq irq); |
| 90 | |
| 91 | #endif |