| 1 | /* |
| 2 | * QEMU CPU model |
| 3 | * |
| 4 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License |
| 8 | * as published by the Free Software Foundation; either version 2 |
| 9 | * of the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, see |
| 18 | * <http://www.gnu.org/licenses/gpl-2.0.html> |
| 19 | */ |
| 20 | #ifndef QEMU_CPU_H |
| 21 | #define QEMU_CPU_H |
| 22 | |
| 23 | #include "hw/core/qdev.h" |
| 24 | #include "disas/dis-asm.h" |
| 25 | #include "exec/breakpoint.h" |
| 26 | #include "exec/hwaddr.h" |
| 27 | #include "exec/vaddr.h" |
| 28 | #include "exec/memattrs.h" |
| 29 | #include "exec/mmu-access-type.h" |
| 30 | #include "exec/tlb-common.h" |
| 31 | #include "qapi/qapi-types-machine.h" |
| 32 | #include "qapi/qapi-types-run-state.h" |
| 33 | #include "qemu/bitmap.h" |
| 34 | #include "qemu/rcu_queue.h" |
| 35 | #include "qemu/queue.h" |
| 36 | #include "qemu/lockcnt.h" |
| 37 | #include "qemu/thread.h" |
| 38 | #include "qom/object.h" |
| 39 | |
| 40 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
| 41 | void *opaque); |
| 42 | |
| 43 | /** |
| 44 | * SECTION:cpu |
| 45 | * @section_id: QEMU-cpu |
| 46 | * @title: CPU Class |
| 47 | * @short_description: Base class for all CPUs |
| 48 | */ |
| 49 | |
| 50 | #define TYPE_CPU "cpu" |
| 51 | |
| 52 | /* Since this macro is used a lot in hot code paths and in conjunction with |
| 53 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using |
| 54 | * an unchecked cast. |
| 55 | */ |
| 56 | #define CPU(obj) ((CPUState *)(obj)) |
| 57 | |
| 58 | /* |
| 59 | * The class checkers bring in CPU_GET_CLASS() which is potentially |
| 60 | * expensive given the eventual call to |
| 61 | * object_class_dynamic_cast_assert(). Because of this the CPUState |
| 62 | * has a cached value for the class in cs->cc which is set up in |
| 63 | * cpu_common_initfn() for use in hot code paths. |
| 64 | */ |
| 65 | typedef struct CPUClass CPUClass; |
| 66 | DECLARE_CLASS_CHECKERS(CPUClass, CPU, |
| 67 | TYPE_CPU) |
| 68 | |
| 69 | /** |
| 70 | * OBJECT_DECLARE_CPU_TYPE: |
| 71 | * @CpuInstanceType: instance struct name |
| 72 | * @CpuClassType: class struct name |
| 73 | * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators |
| 74 | * |
| 75 | * This macro is typically used in "cpu-qom.h" header file, and will: |
| 76 | * |
| 77 | * - create the typedefs for the CPU object and class structs |
| 78 | * - register the type for use with g_autoptr |
| 79 | * - provide three standard type cast functions |
| 80 | * |
| 81 | * The object struct and class struct need to be declared manually. |
| 82 | */ |
| 83 | #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ |
| 84 | typedef struct ArchCPU CpuInstanceType; \ |
| 85 | OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); |
| 86 | |
| 87 | typedef struct CPUWatchpoint CPUWatchpoint; |
| 88 | |
| 89 | /* see physmem.c */ |
| 90 | struct CPUAddressSpace; |
| 91 | |
| 92 | /* see accel/tcg/tb-jmp-cache.h */ |
| 93 | struct CPUJumpCache; |
| 94 | |
| 95 | /* see accel-cpu.h */ |
| 96 | struct AccelCPUClass; |
| 97 | |
| 98 | /* see sysemu-cpu-ops.h */ |
| 99 | struct SysemuCPUOps; |
| 100 | |
| 101 | /** |
| 102 | * CPUClass: |
| 103 | * @class_by_name: Callback to map -cpu command line model name to an |
| 104 | * instantiatable CPU type. |
| 105 | * @list_cpus: list available CPU models and flags. |
| 106 | * @parse_features: Callback to parse command line arguments. |
| 107 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
| 108 | * @memory_rw_debug: Callback for GDB memory access. |
| 109 | * @dump_state: Callback for dumping state. |
| 110 | * @query_cpu_fast: |
| 111 | * Fill in target specific information for the "query-cpus-fast" |
| 112 | * QAPI call. |
| 113 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
| 114 | * @set_pc: Callback for setting the Program Counter register. This |
| 115 | * should have the semantics used by the target architecture when |
| 116 | * setting the PC from a source such as an ELF file entry point; |
| 117 | * for example on Arm it will also set the Thumb mode bit based |
| 118 | * on the least significant bit of the new PC value. |
| 119 | * If the target behaviour here is anything other than "set |
| 120 | * the PC register to the value passed in" then the target must |
| 121 | * also implement the synchronize_from_tb hook. |
| 122 | * @get_pc: Callback for getting the Program Counter register. |
| 123 | * As above, with the semantics of the target architecture. |
| 124 | * @gdb_read_register: Callback for letting GDB read a register. |
| 125 | * No more than @gdb_num_core_regs registers can be read. |
| 126 | * @gdb_write_register: Callback for letting GDB write a register. |
| 127 | * No more than @gdb_num_core_regs registers can be written. |
| 128 | * @gdb_adjust_breakpoint: Callback for adjusting the address of a |
| 129 | * breakpoint. Used by AVR to handle a gdb mis-feature with |
| 130 | * its Harvard architecture split code and data. |
| 131 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
| 132 | * @gdb_num_core_regs: Number of core registers accessible to GDB if no |
| 133 | * @gdb_core_xml_file available (otherwise inferred). |
| 134 | * @gdb_get_core_xml_file: Optional callback that returns the file name for |
| 135 | * the core registers GDB XML description. The returned value is expected to |
| 136 | * be a simple constant string: the caller will not g_free() it. If this |
| 137 | * is NULL then @gdb_core_xml_file will be used instead. |
| 138 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
| 139 | * before the insn which triggers a watchpoint rather than after it. |
| 140 | * @gdb_arch_name: Optional callback that returns the architecture name known |
| 141 | * to GDB. The returned value is expected to be a simple constant string: |
| 142 | * the caller will not g_free() it. |
| 143 | * @disas_set_info: Setup architecture specific components of disassembly info |
| 144 | * @adjust_watchpoint_address: Perform a target-specific adjustment to an |
| 145 | * address before attempting to match it against watchpoints. |
| 146 | * @deprecation_note: If this CPUClass is deprecated, this field provides |
| 147 | * related information. |
| 148 | * @max_as: Maximum valid index used to refer to the address spaces supported by |
| 149 | * the architecture, i.e., to refer to CPUAddressSpaces in |
| 150 | * CPUState::cpu_ases. |
| 151 | * |
| 152 | * Represents a CPU family or model. |
| 153 | */ |
| 154 | struct CPUClass { |
| 155 | /*< private >*/ |
| 156 | DeviceClass parent_class; |
| 157 | /*< public >*/ |
| 158 | |
| 159 | ObjectClass *(*class_by_name)(const char *cpu_model); |
| 160 | void (*list_cpus)(void); |
| 161 | void (*parse_features)(const char *typename, char *str, Error **errp); |
| 162 | |
| 163 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
| 164 | uint8_t *buf, size_t len, bool is_write); |
| 165 | void (*dump_state)(CPUState *cpu, FILE *, int flags); |
| 166 | void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); |
| 167 | int64_t (*get_arch_id)(CPUState *cpu); |
| 168 | void (*set_pc)(CPUState *cpu, vaddr value); |
| 169 | vaddr (*get_pc)(CPUState *cpu); |
| 170 | int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); |
| 171 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); |
| 172 | vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); |
| 173 | |
| 174 | const char *gdb_core_xml_file; |
| 175 | const char * (*gdb_arch_name)(CPUState *cpu); |
| 176 | const char * (*gdb_get_core_xml_file)(CPUState *cpu); |
| 177 | |
| 178 | void (*disas_set_info)(const CPUState *cpu, disassemble_info *info); |
| 179 | |
| 180 | const char *deprecation_note; |
| 181 | struct AccelCPUClass *accel_cpu; |
| 182 | |
| 183 | /* when system emulation is not available, this pointer is NULL */ |
| 184 | const struct SysemuCPUOps *sysemu_ops; |
| 185 | |
| 186 | /* when TCG is not available, this pointer is NULL */ |
| 187 | const TCGCPUOps *tcg_ops; |
| 188 | |
| 189 | /* |
| 190 | * Keep non-pointer data at the end to minimize holes. |
| 191 | */ |
| 192 | int reset_dump_flags; |
| 193 | int gdb_num_core_regs; |
| 194 | bool gdb_stop_before_watchpoint; |
| 195 | |
| 196 | int max_as; |
| 197 | }; |
| 198 | |
| 199 | /* |
| 200 | * Fix the number of mmu modes across all targets. |
| 201 | * Current maximum is target/arm/. |
| 202 | */ |
| 203 | #define NB_MMU_MODES 22 |
| 204 | typedef uint32_t MMUIdxMap; |
| 205 | |
| 206 | /* Use a fully associative victim tlb of 8 entries. */ |
| 207 | #define CPU_VTLB_SIZE 8 |
| 208 | |
| 209 | /* |
| 210 | * The full TLB entry, which is not accessed by generated TCG code, |
| 211 | * so the layout is not as critical as that of CPUTLBEntry. This is |
| 212 | * also why we don't want to combine the two structs. |
| 213 | */ |
| 214 | struct CPUTLBEntryFull { |
| 215 | /* |
| 216 | * @xlat_offset: TARGET_PAGE_BITS aligned offset which must be added to |
| 217 | * the virtual address to obtain: |
| 218 | * + the ram_addr_t of the target RAM (if the physical section |
| 219 | * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) |
| 220 | * + the offset within the target MemoryRegion (otherwise) |
| 221 | */ |
| 222 | hwaddr xlat_offset; |
| 223 | |
| 224 | /* @section contains physical section. */ |
| 225 | MemoryRegionSection *section; |
| 226 | |
| 227 | /* |
| 228 | * @phys_addr contains the physical address in the address space |
| 229 | * given by cpu_asidx_from_attrs(cpu, @attrs). |
| 230 | */ |
| 231 | hwaddr phys_addr; |
| 232 | |
| 233 | /* @attrs contains the memory transaction attributes for the page. */ |
| 234 | MemTxAttrs attrs; |
| 235 | |
| 236 | /* @prot contains the complete protections for the page. */ |
| 237 | uint8_t prot; |
| 238 | |
| 239 | /* @lg_page_size contains the log2 of the page size. */ |
| 240 | uint8_t lg_page_size; |
| 241 | |
| 242 | /* Additional tlb flags requested by tlb_fill. */ |
| 243 | uint8_t tlb_fill_flags; |
| 244 | |
| 245 | /* |
| 246 | * Additional tlb flags for use by the slow path. If non-zero, |
| 247 | * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. |
| 248 | */ |
| 249 | uint8_t slow_flags[MMU_ACCESS_COUNT]; |
| 250 | |
| 251 | /* |
| 252 | * Allow target-specific additions to this structure. |
| 253 | * This may be used to cache items from the guest cpu |
| 254 | * page tables for later use by the implementation. |
| 255 | */ |
| 256 | union { |
| 257 | /* |
| 258 | * Cache the attrs and shareability fields from the page table entry. |
| 259 | * |
| 260 | * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. |
| 261 | * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. |
| 262 | * For shareability and guarded, as in the SH and GP fields respectively |
| 263 | * of the VMSAv8-64 PTEs. |
| 264 | */ |
| 265 | struct { |
| 266 | uint8_t pte_attrs; |
| 267 | uint8_t shareability; |
| 268 | bool guarded; |
| 269 | } arm; |
| 270 | } extra; |
| 271 | }; |
| 272 | |
| 273 | /* |
| 274 | * Data elements that are per MMU mode, minus the bits accessed by |
| 275 | * the TCG fast path. |
| 276 | */ |
| 277 | typedef struct CPUTLBDesc { |
| 278 | /* |
| 279 | * Describe a region covering all of the large pages allocated |
| 280 | * into the tlb. When any page within this region is flushed, |
| 281 | * we must flush the entire tlb. The region is matched if |
| 282 | * (addr & large_page_mask) == large_page_addr. |
| 283 | */ |
| 284 | vaddr large_page_addr; |
| 285 | vaddr large_page_mask; |
| 286 | /* host time (in ns) at the beginning of the time window */ |
| 287 | int64_t window_begin_ns; |
| 288 | /* maximum number of entries observed in the window */ |
| 289 | size_t window_max_entries; |
| 290 | size_t n_used_entries; |
| 291 | /* The next index to use in the tlb victim table. */ |
| 292 | size_t vindex; |
| 293 | /* The tlb victim table, in two parts. */ |
| 294 | CPUTLBEntry vtable[CPU_VTLB_SIZE]; |
| 295 | CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; |
| 296 | CPUTLBEntryFull *fulltlb; |
| 297 | } CPUTLBDesc; |
| 298 | |
| 299 | /* |
| 300 | * Data elements that are shared between all MMU modes. |
| 301 | */ |
| 302 | typedef struct CPUTLBCommon { |
| 303 | /* Serialize updates to f.table and d.vtable, and others as noted. */ |
| 304 | QemuSpin lock; |
| 305 | /* |
| 306 | * Within dirty, for each bit N, modifications have been made to |
| 307 | * mmu_idx N since the last time that mmu_idx was flushed. |
| 308 | * Protected by tlb_c.lock. |
| 309 | */ |
| 310 | MMUIdxMap dirty; |
| 311 | /* |
| 312 | * Statistics. These are not lock protected, but are read and |
| 313 | * written atomically. This allows the monitor to print a snapshot |
| 314 | * of the stats without interfering with the cpu. |
| 315 | */ |
| 316 | size_t full_flush_count; |
| 317 | size_t part_flush_count; |
| 318 | size_t elide_flush_count; |
| 319 | } CPUTLBCommon; |
| 320 | |
| 321 | /* |
| 322 | * The entire softmmu tlb, for all MMU modes. |
| 323 | * The meaning of each of the MMU modes is defined in the target code. |
| 324 | * Since this is placed within CPUNegativeOffsetState, the smallest |
| 325 | * negative offsets are at the end of the struct. |
| 326 | */ |
| 327 | typedef struct CPUTLB { |
| 328 | #ifdef CONFIG_TCG |
| 329 | CPUTLBCommon c; |
| 330 | CPUTLBDesc d[NB_MMU_MODES]; |
| 331 | CPUTLBDescFast f[NB_MMU_MODES]; |
| 332 | #endif |
| 333 | } CPUTLB; |
| 334 | |
| 335 | /* |
| 336 | * Low 16 bits: number of cycles left, used only in icount mode. |
| 337 | * High 16 bits: Set to -1 to force TCG to stop executing linked TBs |
| 338 | * for this CPU and return to its top level loop (even in non-icount mode). |
| 339 | * This allows a single read-compare-cbranch-write sequence to test |
| 340 | * for both decrementer underflow and exceptions. |
| 341 | */ |
| 342 | typedef union IcountDecr { |
| 343 | uint32_t u32; |
| 344 | struct { |
| 345 | #if HOST_BIG_ENDIAN |
| 346 | uint16_t high; |
| 347 | uint16_t low; |
| 348 | #else |
| 349 | uint16_t low; |
| 350 | uint16_t high; |
| 351 | #endif |
| 352 | } u16; |
| 353 | } IcountDecr; |
| 354 | |
| 355 | /** |
| 356 | * CPUNegativeOffsetState: Elements of CPUState most efficiently accessed |
| 357 | * from CPUArchState, via small negative offsets. |
| 358 | * @can_do_io: True if memory-mapped IO is allowed. |
| 359 | * @plugin_mem_cbs: active plugin memory callbacks |
| 360 | * @plugin_mem_value_low: 64 lower bits of latest accessed mem value. |
| 361 | * @plugin_mem_value_high: 64 higher bits of latest accessed mem value. |
| 362 | */ |
| 363 | typedef struct CPUNegativeOffsetState { |
| 364 | CPUTLB tlb; |
| 365 | #ifdef CONFIG_PLUGIN |
| 366 | /* |
| 367 | * The callback pointer are accessed via TCG (see gen_empty_mem_helper). |
| 368 | */ |
| 369 | GArray *plugin_mem_cbs; |
| 370 | uint64_t plugin_mem_value_low; |
| 371 | uint64_t plugin_mem_value_high; |
| 372 | int32_t plugin_cb_flags; |
| 373 | #endif |
| 374 | IcountDecr icount_decr; |
| 375 | bool can_do_io; |
| 376 | } CPUNegativeOffsetState; |
| 377 | |
| 378 | struct KVMState; |
| 379 | struct kvm_run; |
| 380 | |
| 381 | /* work queue */ |
| 382 | |
| 383 | /* The union type allows passing of 64 bit target pointers on 32 bit |
| 384 | * hosts in a single parameter |
| 385 | */ |
| 386 | typedef union { |
| 387 | int host_int; |
| 388 | unsigned long host_ulong; |
| 389 | void *host_ptr; |
| 390 | vaddr target_ptr; |
| 391 | } run_on_cpu_data; |
| 392 | |
| 393 | #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) |
| 394 | #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) |
| 395 | #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) |
| 396 | #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) |
| 397 | #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) |
| 398 | |
| 399 | typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); |
| 400 | |
| 401 | struct qemu_work_item; |
| 402 | |
| 403 | #define CPU_UNSET_NUMA_NODE_ID -1 |
| 404 | |
| 405 | /** |
| 406 | * struct CPUState - common state of one CPU core or thread. |
| 407 | * |
| 408 | * @cpu_index: CPU index (informative). |
| 409 | * @cluster_index: Identifies which cluster this CPU is in. |
| 410 | * For boards which don't define clusters or for "loose" CPUs not assigned |
| 411 | * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will |
| 412 | * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER |
| 413 | * QOM parent. |
| 414 | * Under TCG this value is propagated to @tcg_cflags. |
| 415 | * See TranslationBlock::TCG CF_CLUSTER_MASK. |
| 416 | * @start_powered_off: Indicates whether the CPU starts in powered-off state. |
| 417 | * @tcg_cflags: Pre-computed cflags for this cpu. |
| 418 | * @nr_threads: Number of threads within this CPU core. |
| 419 | * @thread: Host thread details, only live once @created is #true |
| 420 | * @sem: WIN32 only semaphore used only for qtest |
| 421 | * @thread_id: native thread id of vCPU, only live once @created is #true |
| 422 | * @running: #true if CPU is currently running (lockless). |
| 423 | * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; |
| 424 | * valid under cpu_list_lock. |
| 425 | * @created: Indicates whether the CPU thread has been successfully created. |
| 426 | * @halt_cond: condition variable sleeping threads can wait on. |
| 427 | * @exit_request: Another thread requests the CPU to call qemu_process_cpu_events(). |
| 428 | * Should be read only by CPU thread with load-acquire, to synchronize with |
| 429 | * other threads' store-release operation. |
| 430 | * |
| 431 | * In some cases, accelerator-specific code will write exit_request from |
| 432 | * within the same thread, to "bump" the effect of qemu_cpu_kick() to |
| 433 | * the one provided by cpu_exit(), especially when processing interrupt |
| 434 | * flags. In this case, the write and read happen in the same thread |
| 435 | * and the write therefore can use qemu_atomic_set(). |
| 436 | * @interrupt_request: Indicates a pending interrupt request. |
| 437 | * Only used by system emulation. |
| 438 | * @halted: Nonzero if the CPU is in suspended state. |
| 439 | * @stop: Indicates a pending stop request. |
| 440 | * @stopped: Indicates the CPU has been artificially stopped. |
| 441 | * @unplug: Indicates a pending CPU unplug request. |
| 442 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
| 443 | * @singlestep_flags: Flags for single-stepping. |
| 444 | * @icount_extra: Instructions until next timer event. |
| 445 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
| 446 | * AddressSpaces this CPU has) |
| 447 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
| 448 | * only have a single AddressSpace |
| 449 | * @gdb_regs: Additional GDB registers. |
| 450 | * @gdb_num_regs: Number of total registers accessible to GDB. |
| 451 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
| 452 | * @node: QTAILQ of CPUs sharing TB cache. |
| 453 | * @opaque: User data. |
| 454 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
| 455 | * @accel: Pointer to accelerator specific state. |
| 456 | * @vcpu_dirty: Hardware accelerator is not synchronized with QEMU state |
| 457 | * @kvm_fd: vCPU file descriptor for KVM. |
| 458 | * @work_mutex: Lock to prevent multiple access to @work_list. |
| 459 | * @work_list: List of pending asynchronous work. |
| 460 | * @plugin_state: per-CPU plugin state |
| 461 | * @ignore_memory_transaction_failures: Cached copy of the MachineState |
| 462 | * flag of the same name: allows the board to suppress calling of the |
| 463 | * CPU do_transaction_failed hook function. |
| 464 | * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty |
| 465 | * ring is enabled. |
| 466 | * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU |
| 467 | * dirty ring structure. |
| 468 | * |
| 469 | * @neg_align: The CPUState is the common part of a concrete ArchCPU |
| 470 | * which is allocated when an individual CPU instance is created. As |
| 471 | * such care is taken is ensure there is no gap between between |
| 472 | * CPUState and CPUArchState within ArchCPU. |
| 473 | * |
| 474 | * @neg: The architectural register state ("cpu_env") immediately follows |
| 475 | * CPUState in ArchCPU and is passed to TCG code. The @neg structure holds |
| 476 | * some common TCG CPU variables which are accessed with a negative offset |
| 477 | * from cpu_env. |
| 478 | */ |
| 479 | struct CPUState { |
| 480 | /*< private >*/ |
| 481 | DeviceState parent_obj; |
| 482 | /* cache to avoid expensive CPU_GET_CLASS */ |
| 483 | const CPUClass *cc; |
| 484 | /*< public >*/ |
| 485 | |
| 486 | int nr_threads; |
| 487 | |
| 488 | struct QemuThread *thread; |
| 489 | #ifdef _WIN32 |
| 490 | QemuSemaphore sem; |
| 491 | #endif |
| 492 | int thread_id; |
| 493 | bool running, has_waiter; |
| 494 | struct QemuCond *halt_cond; |
| 495 | bool thread_kicked; |
| 496 | bool created; |
| 497 | bool stop; |
| 498 | bool stopped; |
| 499 | |
| 500 | bool start_powered_off; |
| 501 | |
| 502 | bool unplug; |
| 503 | bool crash_occurred; |
| 504 | bool exit_request; |
| 505 | int exclusive_context_count; |
| 506 | uint32_t cflags_next_tb; |
| 507 | uint32_t interrupt_request; |
| 508 | unsigned singlestep_flags; |
| 509 | int64_t icount_budget; |
| 510 | int64_t icount_extra; |
| 511 | uint64_t random_seed; |
| 512 | sigjmp_buf jmp_env; |
| 513 | |
| 514 | QemuMutex work_mutex; |
| 515 | QSIMPLEQ_HEAD(, qemu_work_item) work_list; |
| 516 | |
| 517 | struct CPUAddressSpace *cpu_ases; |
| 518 | AddressSpace *as; |
| 519 | MemoryRegion *memory; |
| 520 | |
| 521 | struct CPUJumpCache *tb_jmp_cache; |
| 522 | |
| 523 | GArray *gdb_regs; |
| 524 | int gdb_num_regs; |
| 525 | int gdb_num_g_regs; |
| 526 | QTAILQ_ENTRY(CPUState) node; |
| 527 | |
| 528 | /* ice debug support */ |
| 529 | QTAILQ_HEAD(, CPUBreakpoint) breakpoints; |
| 530 | |
| 531 | QTAILQ_HEAD(, CPUWatchpoint) watchpoints; |
| 532 | CPUWatchpoint *watchpoint_hit; |
| 533 | |
| 534 | void *opaque; |
| 535 | |
| 536 | /* In order to avoid passing too many arguments to the MMIO helpers, |
| 537 | * we store some rarely used information in the CPU context. |
| 538 | */ |
| 539 | uintptr_t mem_io_pc; |
| 540 | |
| 541 | /* Only used in KVM */ |
| 542 | int kvm_fd; |
| 543 | struct KVMState *kvm_state; |
| 544 | struct kvm_run *kvm_run; |
| 545 | struct kvm_dirty_gfn *kvm_dirty_gfns; |
| 546 | uint32_t kvm_fetch_index; |
| 547 | uint64_t dirty_pages; |
| 548 | int kvm_vcpu_stats_fd; |
| 549 | |
| 550 | /* Use by accel-block: CPU is executing an ioctl() */ |
| 551 | QemuLockCnt in_ioctl_lock; |
| 552 | |
| 553 | #ifdef CONFIG_PLUGIN |
| 554 | CPUPluginState *plugin_state; |
| 555 | #endif |
| 556 | |
| 557 | /* TODO Move common fields from CPUArchState here. */ |
| 558 | int cpu_index; |
| 559 | int cluster_index; |
| 560 | uint32_t tcg_cflags; |
| 561 | uint32_t halted; |
| 562 | int32_t exception_index; |
| 563 | |
| 564 | bool vcpu_dirty; |
| 565 | AccelCPUState *accel; |
| 566 | |
| 567 | /* Used to keep track of an outstanding cpu throttle thread for migration |
| 568 | * autoconverge |
| 569 | */ |
| 570 | bool throttle_thread_scheduled; |
| 571 | |
| 572 | /* |
| 573 | * Sleep throttle_us_per_full microseconds once dirty ring is full |
| 574 | * if dirty page rate limit is enabled. |
| 575 | */ |
| 576 | int64_t throttle_us_per_full; |
| 577 | |
| 578 | bool ignore_memory_transaction_failures; |
| 579 | |
| 580 | /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ |
| 581 | bool prctl_unalign_sigbus; |
| 582 | |
| 583 | /* track IOMMUs whose translations we've cached in the TCG TLB */ |
| 584 | GArray *iommu_notifiers; |
| 585 | |
| 586 | /* |
| 587 | * MUST BE LAST in order to minimize the displacement to CPUArchState. |
| 588 | */ |
| 589 | char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16); |
| 590 | CPUNegativeOffsetState neg; |
| 591 | }; |
| 592 | |
| 593 | /* Validate placement of CPUNegativeOffsetState. */ |
| 594 | QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) != |
| 595 | sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); |
| 596 | |
| 597 | static inline CPUArchState *cpu_env(CPUState *cpu) |
| 598 | { |
| 599 | /* We validate that CPUArchState follows CPUState in cpu-target.c */ |
| 600 | return (CPUArchState *)(cpu + 1); |
| 601 | } |
| 602 | |
| 603 | #ifdef CONFIG_TCG |
| 604 | /* |
| 605 | * Invert the index order of the CPUTLBDescFast array so that lower |
| 606 | * mmu_idx have offsets from env with smaller magnitude. |
| 607 | */ |
| 608 | static inline int mmuidx_to_fast_index(int mmu_idx) |
| 609 | { |
| 610 | return NB_MMU_MODES - 1 - mmu_idx; |
| 611 | } |
| 612 | |
| 613 | static inline CPUTLBDescFast *cpu_tlb_fast(CPUState *cpu, int mmu_idx) |
| 614 | { |
| 615 | return &cpu->neg.tlb.f[mmuidx_to_fast_index(mmu_idx)]; |
| 616 | } |
| 617 | #endif |
| 618 | |
| 619 | typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; |
| 620 | extern CPUTailQ cpus_queue; |
| 621 | |
| 622 | #define first_cpu QTAILQ_FIRST_RCU(&cpus_queue) |
| 623 | #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) |
| 624 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node) |
| 625 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ |
| 626 | QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) |
| 627 | |
| 628 | extern __thread CPUState *current_cpu; |
| 629 | |
| 630 | /** |
| 631 | * cpu_paging_enabled: |
| 632 | * @cpu: The CPU whose state is to be inspected. |
| 633 | * |
| 634 | * Returns: %true if paging is enabled, %false otherwise. |
| 635 | */ |
| 636 | bool cpu_paging_enabled(const CPUState *cpu); |
| 637 | |
| 638 | /** |
| 639 | * cpu_get_memory_mapping: |
| 640 | * @cpu: The CPU whose memory mappings are to be obtained. |
| 641 | * @list: Where to write the memory mappings to. |
| 642 | * @errp: Pointer for reporting an #Error. |
| 643 | * |
| 644 | * Returns: %true on success, %false otherwise. |
| 645 | */ |
| 646 | bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, |
| 647 | Error **errp); |
| 648 | |
| 649 | /** |
| 650 | * cpu_write_elf64_note: |
| 651 | * @f: pointer to a function that writes memory to a file |
| 652 | * @cpu: The CPU whose memory is to be dumped |
| 653 | * @cpuid: ID number of the CPU |
| 654 | * @opaque: pointer to the CPUState struct |
| 655 | */ |
| 656 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, |
| 657 | int cpuid, void *opaque); |
| 658 | |
| 659 | /** |
| 660 | * cpu_write_elf64_qemunote: |
| 661 | * @f: pointer to a function that writes memory to a file |
| 662 | * @cpu: The CPU whose memory is to be dumped |
| 663 | * @cpuid: ID number of the CPU |
| 664 | * @opaque: pointer to the CPUState struct |
| 665 | */ |
| 666 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
| 667 | void *opaque); |
| 668 | |
| 669 | /** |
| 670 | * cpu_write_elf32_note: |
| 671 | * @f: pointer to a function that writes memory to a file |
| 672 | * @cpu: The CPU whose memory is to be dumped |
| 673 | * @cpuid: ID number of the CPU |
| 674 | * @opaque: pointer to the CPUState struct |
| 675 | */ |
| 676 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, |
| 677 | int cpuid, void *opaque); |
| 678 | |
| 679 | /** |
| 680 | * cpu_write_elf32_qemunote: |
| 681 | * @f: pointer to a function that writes memory to a file |
| 682 | * @cpu: The CPU whose memory is to be dumped |
| 683 | * @cpuid: ID number of the CPU |
| 684 | * @opaque: pointer to the CPUState struct |
| 685 | */ |
| 686 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, |
| 687 | void *opaque); |
| 688 | |
| 689 | /** |
| 690 | * cpu_memory_rw_debug: |
| 691 | * @cpu: The CPU whose memory is to be accessed |
| 692 | * @addr: guest virtual address |
| 693 | * @ptr: buffer with the data transferred |
| 694 | * @len: the number of bytes to read or write |
| 695 | * @is_write: indicates the transfer direction |
| 696 | * |
| 697 | * Take a virtual address, convert it to a physical address via |
| 698 | * an MMU lookup using the current settings of the specified CPU, |
| 699 | * and then perform the access (using address_space_rw() for |
| 700 | * reads or address_space_write_rom() for writes). |
| 701 | * |
| 702 | * This function is intended for use by the GDB stub and similar code. |
| 703 | * |
| 704 | * Returns: 0 on success, -1 on error |
| 705 | */ |
| 706 | int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, |
| 707 | void *ptr, size_t len, bool is_write); |
| 708 | |
| 709 | /** |
| 710 | * cpu_get_crash_info: |
| 711 | * @cpu: The CPU to get crash information for |
| 712 | * |
| 713 | * Gets the previously saved crash information. |
| 714 | * Caller is responsible for freeing the data. |
| 715 | */ |
| 716 | GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); |
| 717 | |
| 718 | /** |
| 719 | * CPUDumpFlags: |
| 720 | * @CPU_DUMP_CODE: |
| 721 | * @CPU_DUMP_FPU: dump FPU register state, not just integer |
| 722 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state |
| 723 | * @CPU_DUMP_VPU: dump VPU registers |
| 724 | */ |
| 725 | enum CPUDumpFlags { |
| 726 | CPU_DUMP_CODE = 0x00010000, |
| 727 | CPU_DUMP_FPU = 0x00020000, |
| 728 | CPU_DUMP_CCOP = 0x00040000, |
| 729 | CPU_DUMP_VPU = 0x00080000, |
| 730 | }; |
| 731 | |
| 732 | /** |
| 733 | * cpu_dump_state: |
| 734 | * @cpu: The CPU whose state is to be dumped. |
| 735 | * @f: If non-null, dump to this stream, else to current print sink. |
| 736 | * |
| 737 | * Dumps CPU state. |
| 738 | */ |
| 739 | void cpu_dump_state(CPUState *cpu, FILE *f, int flags); |
| 740 | |
| 741 | /** |
| 742 | * TranslateForDebugResult: gives result of cpu_translate_for_debug() |
| 743 | * |
| 744 | * @physaddr: the physical address corresponding to the virtual address |
| 745 | * @attrs: the transaction attributes for this access |
| 746 | * @lg_page_size: log2 of the size of the aligned block of memory |
| 747 | * that this physaddr and attrs are valid for. |
| 748 | */ |
| 749 | typedef struct TranslateForDebugResult { |
| 750 | hwaddr physaddr; |
| 751 | MemTxAttrs attrs; |
| 752 | uint8_t lg_page_size; |
| 753 | } TranslateForDebugResult; |
| 754 | |
| 755 | /** |
| 756 | * cpu_translate_for_debug: |
| 757 | * @cpu: The CPU use for the virtual-to-physical translation |
| 758 | * @addr: The virtual address |
| 759 | * @result: Struct filled in with results of translation |
| 760 | * |
| 761 | * Perform a virtual-to-physical address translation for debug accesses. |
| 762 | * Use it only for debugging because no protection checks are done. |
| 763 | * |
| 764 | * The address need not be page-aligned; the returned address in @result |
| 765 | * will be the physical address corresponding to that virtual address. |
| 766 | * |
| 767 | * Returns: false on translation failure; true on successful translation |
| 768 | * and fills in the fields of @result. |
| 769 | */ |
| 770 | bool cpu_translate_for_debug(CPUState *cpu, vaddr addr, |
| 771 | TranslateForDebugResult *result); |
| 772 | |
| 773 | /** cpu_asidx_from_attrs: |
| 774 | * @cpu: CPU |
| 775 | * @attrs: memory transaction attributes |
| 776 | * |
| 777 | * Returns the address space index specifying the CPU AddressSpace |
| 778 | * to use for a memory access with the given transaction attributes. |
| 779 | */ |
| 780 | int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); |
| 781 | |
| 782 | /** |
| 783 | * cpu_internal_is_big_endian: |
| 784 | * @cpu: CPU |
| 785 | |
| 786 | * Returns %true if a CPU which supports runtime configurable endianness |
| 787 | * is currently big-endian. |
| 788 | */ |
| 789 | bool cpu_internal_is_big_endian(CPUState *cpu); |
| 790 | |
| 791 | /** |
| 792 | * cpu_has_work: |
| 793 | * @cpu: The vCPU to check. |
| 794 | * |
| 795 | * Checks whether the CPU has work to do. |
| 796 | * |
| 797 | * Returns: %true if the CPU has work, %false otherwise. |
| 798 | */ |
| 799 | bool cpu_has_work(CPUState *cpu); |
| 800 | |
| 801 | /** |
| 802 | * cpu_list_add: |
| 803 | * @cpu: The CPU to be added to the list of CPUs. |
| 804 | */ |
| 805 | void cpu_list_add(CPUState *cpu); |
| 806 | |
| 807 | /** |
| 808 | * cpu_list_remove: |
| 809 | * @cpu: The CPU to be removed from the list of CPUs. |
| 810 | */ |
| 811 | void cpu_list_remove(CPUState *cpu); |
| 812 | |
| 813 | /** |
| 814 | * cpu_reset: |
| 815 | * @cpu: The CPU whose state is to be reset. |
| 816 | * |
| 817 | * You should refrain from calling this during CPU realization and |
| 818 | * make sure this is called from the reset logic instead. |
| 819 | */ |
| 820 | void cpu_reset(CPUState *cpu); |
| 821 | |
| 822 | /** |
| 823 | * cpu_class_by_name: |
| 824 | * @typename: The CPU base type. |
| 825 | * @cpu_model: The model string without any parameters. |
| 826 | * |
| 827 | * Looks up a concrete CPU #ObjectClass matching name @cpu_model. |
| 828 | * |
| 829 | * Returns: A concrete #CPUClass or %NULL if no matching class is found |
| 830 | * or if the matching class is abstract. |
| 831 | */ |
| 832 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); |
| 833 | |
| 834 | /** |
| 835 | * cpu_model_from_type: |
| 836 | * @typename: The CPU type name |
| 837 | * |
| 838 | * Extract the CPU model name from the CPU type name. The |
| 839 | * CPU type name is either the combination of the CPU model |
| 840 | * name and suffix, or same to the CPU model name. |
| 841 | * |
| 842 | * Returns: CPU model name or NULL if the CPU class doesn't exist |
| 843 | * The user should g_free() the string once no longer needed. |
| 844 | */ |
| 845 | char *cpu_model_from_type(const char *typename); |
| 846 | |
| 847 | /** |
| 848 | * cpu_create: |
| 849 | * @typename: The CPU type. |
| 850 | * |
| 851 | * Instantiates a CPU and realizes the CPU. |
| 852 | * |
| 853 | * Returns: A #CPUState or %NULL if an error occurred. |
| 854 | */ |
| 855 | CPUState *cpu_create(const char *typename); |
| 856 | |
| 857 | /** |
| 858 | * parse_cpu_option: |
| 859 | * @cpu_option: The -cpu option including optional parameters. |
| 860 | * |
| 861 | * processes optional parameters and registers them as global properties |
| 862 | * |
| 863 | * Returns: type of CPU to create or prints error and terminates process |
| 864 | * if an error occurred. |
| 865 | */ |
| 866 | const char *parse_cpu_option(const char *cpu_option); |
| 867 | |
| 868 | /** |
| 869 | * qemu_cpu_is_self: |
| 870 | * @cpu: The vCPU to check against. |
| 871 | * |
| 872 | * Checks whether the caller is executing on the vCPU thread. |
| 873 | * |
| 874 | * Returns: %true if called from @cpu's thread, %false otherwise. |
| 875 | */ |
| 876 | bool qemu_cpu_is_self(CPUState *cpu); |
| 877 | |
| 878 | /** |
| 879 | * qemu_cpu_kick: |
| 880 | * @cpu: The vCPU to kick. |
| 881 | * |
| 882 | * Kicks @cpu's thread to exit the accelerator. For accelerators that |
| 883 | * can do that, the target vCPU thread will try not to take the BQL. |
| 884 | */ |
| 885 | void qemu_cpu_kick(CPUState *cpu); |
| 886 | |
| 887 | /** |
| 888 | * cpu_is_stopped: |
| 889 | * @cpu: The CPU to check. |
| 890 | * |
| 891 | * Checks whether the CPU is stopped. |
| 892 | * |
| 893 | * Returns: %true if run state is not running or if artificially stopped; |
| 894 | * %false otherwise. |
| 895 | */ |
| 896 | bool cpu_is_stopped(CPUState *cpu); |
| 897 | |
| 898 | /** |
| 899 | * do_run_on_cpu: |
| 900 | * @cpu: The vCPU to run on. |
| 901 | * @func: The function to be executed. |
| 902 | * @data: Data to pass to the function. |
| 903 | * @mutex: Mutex to release while waiting for @func to run. |
| 904 | * |
| 905 | * Used internally in the implementation of run_on_cpu. |
| 906 | */ |
| 907 | void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, |
| 908 | QemuMutex *mutex); |
| 909 | |
| 910 | /** |
| 911 | * run_on_cpu: |
| 912 | * @cpu: The vCPU to run on. |
| 913 | * @func: The function to be executed. |
| 914 | * @data: Data to pass to the function. |
| 915 | * |
| 916 | * Schedules the function @func for execution on the vCPU @cpu. |
| 917 | */ |
| 918 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
| 919 | |
| 920 | /** |
| 921 | * async_run_on_cpu: |
| 922 | * @cpu: The vCPU to run on. |
| 923 | * @func: The function to be executed. |
| 924 | * @data: Data to pass to the function. |
| 925 | * |
| 926 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. |
| 927 | */ |
| 928 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
| 929 | |
| 930 | /** |
| 931 | * async_safe_run_on_cpu: |
| 932 | * @cpu: The vCPU to run on. |
| 933 | * @func: The function to be executed. |
| 934 | * @data: Data to pass to the function. |
| 935 | * |
| 936 | * Schedules the function @func for execution on the vCPU @cpu asynchronously, |
| 937 | * while all other vCPUs are sleeping. |
| 938 | * |
| 939 | * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the |
| 940 | * BQL. |
| 941 | */ |
| 942 | void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); |
| 943 | |
| 944 | /** |
| 945 | * cpu_in_exclusive_context() |
| 946 | * @cpu: The vCPU to check |
| 947 | * |
| 948 | * Returns true if @cpu is an exclusive context, for example running |
| 949 | * something which has previously been queued via async_safe_run_on_cpu(). |
| 950 | */ |
| 951 | static inline bool cpu_in_exclusive_context(const CPUState *cpu) |
| 952 | { |
| 953 | return cpu->exclusive_context_count; |
| 954 | } |
| 955 | |
| 956 | /** |
| 957 | * qemu_get_cpu: |
| 958 | * @index: The CPUState@cpu_index value of the CPU to obtain. |
| 959 | * |
| 960 | * Gets a CPU matching @index. |
| 961 | * |
| 962 | * Returns: The CPU or %NULL if there is no matching CPU. |
| 963 | */ |
| 964 | CPUState *qemu_get_cpu(int index); |
| 965 | |
| 966 | /** |
| 967 | * cpu_exists: |
| 968 | * @id: Guest-exposed CPU ID to lookup. |
| 969 | * |
| 970 | * Search for CPU with specified ID. |
| 971 | * |
| 972 | * Returns: %true - CPU is found, %false - CPU isn't found. |
| 973 | */ |
| 974 | bool cpu_exists(int64_t id); |
| 975 | |
| 976 | /** |
| 977 | * cpu_by_arch_id: |
| 978 | * @id: Guest-exposed CPU ID of the CPU to obtain. |
| 979 | * |
| 980 | * Get a CPU with matching @id. |
| 981 | * |
| 982 | * Returns: The CPU or %NULL if there is no matching CPU. |
| 983 | */ |
| 984 | CPUState *cpu_by_arch_id(int64_t id); |
| 985 | |
| 986 | /** |
| 987 | * cpu_interrupt: |
| 988 | * @cpu: The CPU to set an interrupt on. |
| 989 | * @mask: The interrupts to set. |
| 990 | * |
| 991 | * Invokes the interrupt handler. |
| 992 | */ |
| 993 | |
| 994 | void cpu_interrupt(CPUState *cpu, int mask); |
| 995 | |
| 996 | /** |
| 997 | * cpu_test_interrupt: |
| 998 | * @cpu: The CPU to check interrupt(s) on. |
| 999 | * @mask: The interrupts to check. |
| 1000 | * |
| 1001 | * Checks if any of interrupts in @mask are pending on @cpu. |
| 1002 | */ |
| 1003 | static inline bool cpu_test_interrupt(CPUState *cpu, int mask) |
| 1004 | { |
| 1005 | return qatomic_load_acquire(&cpu->interrupt_request) & mask; |
| 1006 | } |
| 1007 | |
| 1008 | /** |
| 1009 | * cpu_set_interrupt: |
| 1010 | * @cpu: The CPU to set pending interrupt(s) on. |
| 1011 | * @mask: The interrupts to set. |
| 1012 | * |
| 1013 | * Sets interrupts in @mask as pending on @cpu. Unlike @cpu_interrupt, |
| 1014 | * this does not kick the vCPU. |
| 1015 | */ |
| 1016 | void cpu_set_interrupt(CPUState *cpu, int mask); |
| 1017 | |
| 1018 | /** |
| 1019 | * cpu_set_pc: |
| 1020 | * @cpu: The CPU to set the program counter for. |
| 1021 | * @addr: Program counter value. |
| 1022 | * |
| 1023 | * Sets the program counter for a CPU. |
| 1024 | */ |
| 1025 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) |
| 1026 | { |
| 1027 | cpu->cc->set_pc(cpu, addr); |
| 1028 | } |
| 1029 | |
| 1030 | /** |
| 1031 | * cpu_reset_interrupt: |
| 1032 | * @cpu: The CPU to clear the interrupt on. |
| 1033 | * @mask: The interrupt mask to clear. |
| 1034 | * |
| 1035 | * Resets interrupts on the vCPU @cpu. |
| 1036 | */ |
| 1037 | void cpu_reset_interrupt(CPUState *cpu, int mask); |
| 1038 | |
| 1039 | /** |
| 1040 | * cpu_exit: |
| 1041 | * @cpu: The CPU to exit. |
| 1042 | * |
| 1043 | * Requests the CPU @cpu to exit execution. |
| 1044 | */ |
| 1045 | void cpu_exit(CPUState *cpu); |
| 1046 | |
| 1047 | /** |
| 1048 | * cpu_pause: |
| 1049 | * @cpu: The CPU to pause. |
| 1050 | * |
| 1051 | * Pauses CPU, i.e. puts CPU into stopped state. |
| 1052 | */ |
| 1053 | void cpu_pause(CPUState *cpu); |
| 1054 | |
| 1055 | /** |
| 1056 | * cpu_resume: |
| 1057 | * @cpu: The CPU to resume. |
| 1058 | * |
| 1059 | * Resumes CPU, i.e. puts CPU into runnable state. |
| 1060 | */ |
| 1061 | void cpu_resume(CPUState *cpu); |
| 1062 | |
| 1063 | /** |
| 1064 | * cpu_remove_sync: |
| 1065 | * @cpu: The CPU to remove. |
| 1066 | * |
| 1067 | * Requests the CPU to be removed and waits till it is removed. |
| 1068 | */ |
| 1069 | void cpu_remove_sync(CPUState *cpu); |
| 1070 | |
| 1071 | /** |
| 1072 | * free_queued_cpu_work() - free all items on CPU work queue |
| 1073 | * @cpu: The CPU which work queue to free. |
| 1074 | */ |
| 1075 | void free_queued_cpu_work(CPUState *cpu); |
| 1076 | |
| 1077 | /** |
| 1078 | * process_queued_cpu_work() - process all items on CPU work queue |
| 1079 | * @cpu: The CPU which work queue to process. |
| 1080 | */ |
| 1081 | void process_queued_cpu_work(CPUState *cpu); |
| 1082 | |
| 1083 | /** |
| 1084 | * cpu_exec_start: |
| 1085 | * @cpu: The CPU for the current thread. |
| 1086 | * |
| 1087 | * Record that a CPU has started execution and can be interrupted with |
| 1088 | * cpu_exit. |
| 1089 | */ |
| 1090 | void cpu_exec_start(CPUState *cpu); |
| 1091 | |
| 1092 | /** |
| 1093 | * cpu_exec_end: |
| 1094 | * @cpu: The CPU for the current thread. |
| 1095 | * |
| 1096 | * Record that a CPU has stopped execution and exclusive sections |
| 1097 | * can be executed without interrupting it. |
| 1098 | */ |
| 1099 | void cpu_exec_end(CPUState *cpu); |
| 1100 | |
| 1101 | /** |
| 1102 | * start_exclusive: |
| 1103 | * |
| 1104 | * Wait for a concurrent exclusive section to end, and then start |
| 1105 | * a section of work that is run while other CPUs are not running |
| 1106 | * between cpu_exec_start and cpu_exec_end. CPUs that are running |
| 1107 | * cpu_exec are exited immediately. CPUs that call cpu_exec_start |
| 1108 | * during the exclusive section go to sleep until this CPU calls |
| 1109 | * end_exclusive. |
| 1110 | */ |
| 1111 | void start_exclusive(void); |
| 1112 | |
| 1113 | /** |
| 1114 | * end_exclusive: |
| 1115 | * |
| 1116 | * Concludes an exclusive execution section started by start_exclusive. |
| 1117 | */ |
| 1118 | void end_exclusive(void); |
| 1119 | |
| 1120 | /** |
| 1121 | * qemu_init_vcpu: |
| 1122 | * @cpu: The vCPU to initialize. |
| 1123 | * |
| 1124 | * Initializes a vCPU. |
| 1125 | */ |
| 1126 | void qemu_init_vcpu(CPUState *cpu); |
| 1127 | |
| 1128 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
| 1129 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
| 1130 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
| 1131 | |
| 1132 | /** |
| 1133 | * cpu_single_step: |
| 1134 | * @cpu: CPU to the flags for. |
| 1135 | * @flags: Flags to enable. |
| 1136 | * |
| 1137 | * Enables or disables single-stepping for @cpu. |
| 1138 | */ |
| 1139 | void cpu_single_step(CPUState *cpu, unsigned flags); |
| 1140 | |
| 1141 | /** |
| 1142 | * cpu_single_stepping: |
| 1143 | * @cpu: The vCPU to check |
| 1144 | * |
| 1145 | * Returns whether the vCPU has single-stepping enabled. |
| 1146 | */ |
| 1147 | static inline bool cpu_single_stepping(const CPUState *cpu) |
| 1148 | { |
| 1149 | return cpu->singlestep_flags & SSTEP_ENABLE; |
| 1150 | } |
| 1151 | |
| 1152 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, |
| 1153 | CPUBreakpoint **breakpoint); |
| 1154 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); |
| 1155 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); |
| 1156 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); |
| 1157 | bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask); |
| 1158 | |
| 1159 | /** |
| 1160 | * cpu_get_address_space: |
| 1161 | * @cpu: CPU to get address space from |
| 1162 | * @asidx: index identifying which address space to get |
| 1163 | * |
| 1164 | * Return the requested address space of this CPU. @asidx |
| 1165 | * specifies which address space to read. |
| 1166 | */ |
| 1167 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); |
| 1168 | |
| 1169 | G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) |
| 1170 | G_GNUC_PRINTF(2, 3); |
| 1171 | |
| 1172 | /** |
| 1173 | * qemu_process_cpu_events: |
| 1174 | * @cpu: CPU that left the execution loop |
| 1175 | * |
| 1176 | * Perform accelerator-independent work after the CPU has left |
| 1177 | * the inner execution loop. |
| 1178 | */ |
| 1179 | void qemu_process_cpu_events(CPUState *cpu); |
| 1180 | |
| 1181 | /** cpu_common_realize: CPU DeviceRealize common handler */ |
| 1182 | bool cpu_common_realize(CPUState *cpu, Error **errp); |
| 1183 | /** cpu_common_realize: CPU DeviceUnrealize common handler */ |
| 1184 | void cpu_common_unrealize(CPUState *cpu); |
| 1185 | |
| 1186 | void cpu_exec_reset_hold(CPUState *cpu); |
| 1187 | |
| 1188 | extern const VMStateDescription vmstate_cpu_common; |
| 1189 | |
| 1190 | #define UNASSIGNED_CPU_INDEX -1 |
| 1191 | #define UNASSIGNED_CLUSTER_INDEX -1 |
| 1192 | |
| 1193 | enum CacheType { |
| 1194 | DATA_CACHE, |
| 1195 | INSTRUCTION_CACHE, |
| 1196 | UNIFIED_CACHE |
| 1197 | }; |
| 1198 | |
| 1199 | struct CPUCoreCaches { |
| 1200 | enum CacheType type; |
| 1201 | uint32_t sets; |
| 1202 | uint32_t size; |
| 1203 | uint32_t level; |
| 1204 | uint16_t linesize; |
| 1205 | uint8_t attributes; /* write policy: 0x0 write back, 0x1 write through */ |
| 1206 | uint8_t associativity; |
| 1207 | }; |
| 1208 | |
| 1209 | typedef struct CPUCoreCaches CPUCoreCaches; |
| 1210 | |
| 1211 | #endif |