| 1 | /* |
| 2 | * QEMU CXL Component |
| 3 | * |
| 4 | * Copyright (c) 2020 Intel |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef CXL_COMPONENT_H |
| 11 | #define CXL_COMPONENT_H |
| 12 | |
| 13 | /* CXL r3.1 Section 8.2.4: CXL.cache and CXL.mem Registers */ |
| 14 | #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 |
| 15 | #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 |
| 16 | #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 |
| 17 | |
| 18 | #include "qemu/range.h" |
| 19 | #include "hw/cxl/cxl_cdat.h" |
| 20 | #include "hw/core/register.h" |
| 21 | #include "qapi/error.h" |
| 22 | |
| 23 | enum reg_type { |
| 24 | CXL2_DEVICE, |
| 25 | CXL2_TYPE3_DEVICE, |
| 26 | CXL2_LOGICAL_DEVICE, |
| 27 | CXL2_ROOT_PORT, |
| 28 | CXL2_RC, |
| 29 | CXL2_UPSTREAM_PORT, |
| 30 | CXL2_DOWNSTREAM_PORT, |
| 31 | CXL3_SWITCH_MAILBOX_CCI, |
| 32 | }; |
| 33 | |
| 34 | /* |
| 35 | * CXL r3.2 - 8.2.4 Table 8-22 and 8-23 |
| 36 | * |
| 37 | * Capability registers are defined at the top of the CXL.cache/mem region. |
| 38 | * They are defined to be packed and at variable offsets. However, NULL |
| 39 | * capabilities can be added to the packed array. To facilitate easier access |
| 40 | * within the QEMU code, define these at specified offsets. Then NULL out any |
| 41 | * capabilities for devices which don't (or can't) have a particular capability |
| 42 | * (see cxl_component_register_init_common). NULL capabilities are to be |
| 43 | * ignored by software. |
| 44 | * |
| 45 | * 'offsets' are based on index's which can then be used to report the array |
| 46 | * size in CXL Capability Header Register (index/offset 0). |
| 47 | * |
| 48 | * See CXL r3.2 Table 8-25 for an example of allowing a 'NULL' header. |
| 49 | */ |
| 50 | |
| 51 | /* CXL r3.1 Section 8.2.4.1: CXL Capability Header Register */ |
| 52 | #define CXL_CAPABILITY_VERSION 1 |
| 53 | REG32(CXL_CAPABILITY_HEADER, 0) |
| 54 | FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) |
| 55 | FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) |
| 56 | FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) |
| 57 | FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) |
| 58 | |
| 59 | #define CXLx_CAPABILITY_HEADER(type, idx) \ |
| 60 | enum { CXL_##type##_CAP_HDR_IDX = idx }; \ |
| 61 | REG32(CXL_##type##_CAPABILITY_HEADER, (idx * 0x4)) \ |
| 62 | FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ |
| 63 | FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ |
| 64 | FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) |
| 65 | CXLx_CAPABILITY_HEADER(RAS, 1) |
| 66 | CXLx_CAPABILITY_HEADER(LINK, 2) |
| 67 | CXLx_CAPABILITY_HEADER(HDM, 3) |
| 68 | CXLx_CAPABILITY_HEADER(EXTSEC, 4) |
| 69 | CXLx_CAPABILITY_HEADER(SNOOP, 5) |
| 70 | CXLx_CAPABILITY_HEADER(BI_RT, 6) |
| 71 | CXLx_CAPABILITY_HEADER(BI_DECODER, 7) |
| 72 | |
| 73 | /* |
| 74 | * Capability structures contain the actual registers that the CXL component |
| 75 | * implements. Some of these are specific to certain types of components, but |
| 76 | * this implementation leaves enough space regardless. |
| 77 | */ |
| 78 | |
| 79 | /* CXL r3.1 Section 8.2.4.17: CXL RAS Capability Structure */ |
| 80 | #define CXL_RAS_CAPABILITY_VERSION 3 |
| 81 | /* Give ample space for caps before this */ |
| 82 | #define CXL_RAS_REGISTERS_OFFSET 0x80 |
| 83 | #define CXL_RAS_REGISTERS_SIZE 0x58 |
| 84 | REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) |
| 85 | #define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0 |
| 86 | #define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1 |
| 87 | #define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2 |
| 88 | #define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3 |
| 89 | #define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4 |
| 90 | #define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5 |
| 91 | #define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6 |
| 92 | #define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7 |
| 93 | #define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8 |
| 94 | #define CXL_RAS_UNC_ERR_RSVD_ENCODING 9 |
| 95 | #define CXL_RAS_UNC_ERR_POISON_RECEIVED 10 |
| 96 | #define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11 |
| 97 | #define CXL_RAS_UNC_ERR_INTERNAL 14 |
| 98 | #define CXL_RAS_UNC_ERR_CXL_IDE_TX 15 |
| 99 | #define CXL_RAS_UNC_ERR_CXL_IDE_RX 16 |
| 100 | #define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */ |
| 101 | REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) |
| 102 | REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) |
| 103 | REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) |
| 104 | #define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0 |
| 105 | #define CXL_RAS_COR_ERR_MEM_DATA_ECC 1 |
| 106 | #define CXL_RAS_COR_ERR_CRC_THRESHOLD 2 |
| 107 | #define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3 |
| 108 | #define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4 |
| 109 | #define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5 |
| 110 | #define CXL_RAS_COR_ERR_PHYSICAL 6 |
| 111 | REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) |
| 112 | REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) |
| 113 | FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6) |
| 114 | FIELD(CXL_RAS_ERR_CAP_CTRL, MULTIPLE_HEADER_RECORDING_CAP, 9, 1) |
| 115 | FIELD(CXL_RAS_ERR_POISON_ENABLED, POISON_ENABLED, 13, 1) |
| 116 | REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) |
| 117 | #define CXL_RAS_ERR_HEADER_NUM 32 |
| 118 | /* Offset 0x18 - 0x58 reserved for RAS logs */ |
| 119 | |
| 120 | /* CXL r3.1 Section 8.2.4.18: CXL Security Capability Structure */ |
| 121 | #define CXL_SEC_REGISTERS_OFFSET \ |
| 122 | (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) |
| 123 | #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ |
| 124 | |
| 125 | /* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */ |
| 126 | #define CXL_LINK_CAPABILITY_VERSION 2 |
| 127 | #define CXL_LINK_REGISTERS_OFFSET \ |
| 128 | (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) |
| 129 | #define CXL_LINK_REGISTERS_SIZE 0x50 |
| 130 | |
| 131 | /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */ |
| 132 | #define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */ |
| 133 | #define CXL_HDM_CAPABILITY_VERSION 3 |
| 134 | #define CXL_HDM_REGISTERS_OFFSET \ |
| 135 | (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) |
| 136 | #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) |
| 137 | #define HDM_DECODER_INIT(n) \ |
| 138 | REG32(CXL_HDM_DECODER##n##_BASE_LO, \ |
| 139 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \ |
| 140 | FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \ |
| 141 | REG32(CXL_HDM_DECODER##n##_BASE_HI, \ |
| 142 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \ |
| 143 | REG32(CXL_HDM_DECODER##n##_SIZE_LO, \ |
| 144 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \ |
| 145 | REG32(CXL_HDM_DECODER##n##_SIZE_HI, \ |
| 146 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \ |
| 147 | REG32(CXL_HDM_DECODER##n##_CTRL, \ |
| 148 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \ |
| 149 | FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \ |
| 150 | FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \ |
| 151 | FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \ |
| 152 | FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \ |
| 153 | FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ |
| 154 | FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ |
| 155 | FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ |
| 156 | FIELD(CXL_HDM_DECODER##n##_CTRL, BI, 13, 1) \ |
| 157 | FIELD(CXL_HDM_DECODER##n##_CTRL, UIO, 14, 1) \ |
| 158 | FIELD(CXL_HDM_DECODER##n##_CTRL, UIG, 16, 4) \ |
| 159 | FIELD(CXL_HDM_DECODER##n##_CTRL, UIW, 20, 4) \ |
| 160 | FIELD(CXL_HDM_DECODER##n##_CTRL, ISP, 24, 4) \ |
| 161 | REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ |
| 162 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ |
| 163 | REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ |
| 164 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) \ |
| 165 | REG32(CXL_HDM_DECODER##n##_DPA_SKIP_LO, \ |
| 166 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ |
| 167 | REG32(CXL_HDM_DECODER##n##_DPA_SKIP_HI, \ |
| 168 | CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) |
| 169 | |
| 170 | REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) |
| 171 | FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) |
| 172 | FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) |
| 173 | FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) |
| 174 | FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) |
| 175 | FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) |
| 176 | FIELD(CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 11, 1) |
| 177 | FIELD(CXL_HDM_DECODER_CAPABILITY, 16_WAY, 12, 1) |
| 178 | FIELD(CXL_HDM_DECODER_CAPABILITY, UIO, 13, 1) |
| 179 | FIELD(CXL_HDM_DECODER_CAPABILITY, UIO_DECODER_COUNT, 16, 4) |
| 180 | FIELD(CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 20, 1) |
| 181 | FIELD(CXL_HDM_DECODER_CAPABILITY, SUPPORTED_COHERENCY_MODEL, 21, 2) |
| 182 | REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) |
| 183 | FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) |
| 184 | FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) |
| 185 | |
| 186 | /* Support 4 decoders at all levels of topology */ |
| 187 | #define CXL_HDM_DECODER_COUNT 4 |
| 188 | |
| 189 | HDM_DECODER_INIT(0); |
| 190 | HDM_DECODER_INIT(1); |
| 191 | HDM_DECODER_INIT(2); |
| 192 | HDM_DECODER_INIT(3); |
| 193 | |
| 194 | /* |
| 195 | * CXL r3.1 Section 8.2.4.21: CXL Extended Security Capability Structure |
| 196 | * (Root complex only) |
| 197 | */ |
| 198 | #define EXTSEC_ENTRY_MAX 256 |
| 199 | #define CXL_EXTSEC_CAP_VERSION 2 |
| 200 | #define CXL_EXTSEC_REGISTERS_OFFSET \ |
| 201 | (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE) |
| 202 | #define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) |
| 203 | |
| 204 | /* CXL r3.1 Section 8.2.4.22: CXL IDE Capability Structure */ |
| 205 | #define CXL_IDE_CAP_VERSION 2 |
| 206 | #define CXL_IDE_REGISTERS_OFFSET \ |
| 207 | (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE) |
| 208 | #define CXL_IDE_REGISTERS_SIZE 0x24 |
| 209 | |
| 210 | /* CXL r3.1 Section 8.2.4.23 - CXL Snoop Filter Capability Structure */ |
| 211 | #define CXL_SNOOP_CAP_VERSION 1 |
| 212 | #define CXL_SNOOP_REGISTERS_OFFSET \ |
| 213 | (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) |
| 214 | #define CXL_SNOOP_REGISTERS_SIZE 0x8 |
| 215 | |
| 216 | #define CXL_BI_RT_CAP_VERSION 1 |
| 217 | #define CXL_BI_RT_REGISTERS_OFFSET \ |
| 218 | (CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) |
| 219 | #define CXL_BI_RT_REGISTERS_SIZE 0xC |
| 220 | |
| 221 | REG32(CXL_BI_RT_CAPABILITY, CXL_BI_RT_REGISTERS_OFFSET) |
| 222 | FIELD(CXL_BI_RT_CAPABILITY, EXPLICIT_COMMIT, 0, 1) |
| 223 | REG32(CXL_BI_RT_CTRL, CXL_BI_RT_REGISTERS_OFFSET + 0x4) |
| 224 | FIELD(CXL_BI_RT_CTRL, COMMIT, 0, 1) |
| 225 | REG32(CXL_BI_RT_STATUS, CXL_BI_RT_REGISTERS_OFFSET + 0x8) |
| 226 | FIELD(CXL_BI_RT_STATUS, COMMITTED, 0, 1) |
| 227 | FIELD(CXL_BI_RT_STATUS, ERR_NOT_COMMITTED, 1, 1) |
| 228 | FIELD(CXL_BI_RT_STATUS, COMMIT_TMO_SCALE, 8, 4) |
| 229 | FIELD(CXL_BI_RT_STATUS, COMMIT_TMO_BASE, 12, 4) |
| 230 | |
| 231 | /* CXL r3.2 8.2.4.27 - CXL BI Decoder Capability Structure */ |
| 232 | #define CXL_BI_DECODER_CAP_VERSION 1 |
| 233 | #define CXL_BI_DECODER_REGISTERS_OFFSET \ |
| 234 | (CXL_BI_RT_REGISTERS_OFFSET + CXL_BI_RT_REGISTERS_SIZE) |
| 235 | #define CXL_BI_DECODER_REGISTERS_SIZE 0xC |
| 236 | |
| 237 | REG32(CXL_BI_DECODER_CAPABILITY, CXL_BI_DECODER_REGISTERS_OFFSET) |
| 238 | FIELD(CXL_BI_DECODER_CAPABILITY, HDM_D, 0, 1) |
| 239 | FIELD(CXL_BI_DECODER_CAPABILITY, EXPLICIT_COMMIT, 1, 1) |
| 240 | REG32(CXL_BI_DECODER_CTRL, CXL_BI_DECODER_REGISTERS_OFFSET + 0x4) |
| 241 | FIELD(CXL_BI_DECODER_CTRL, BI_FW, 0, 1) |
| 242 | FIELD(CXL_BI_DECODER_CTRL, BI_ENABLE, 1, 1) |
| 243 | FIELD(CXL_BI_DECODER_CTRL, COMMIT, 2, 1) |
| 244 | REG32(CXL_BI_DECODER_STATUS, CXL_BI_DECODER_REGISTERS_OFFSET + 0x8) |
| 245 | FIELD(CXL_BI_DECODER_STATUS, COMMITTED, 0, 1) |
| 246 | FIELD(CXL_BI_DECODER_STATUS, ERR_NOT_COMMITTED, 1, 1) |
| 247 | FIELD(CXL_BI_DECODER_STATUS, COMMIT_TMO_SCALE, 8, 4) |
| 248 | FIELD(CXL_BI_DECODER_STATUS, COMMIT_TMO_BASE, 12, 4) |
| 249 | |
| 250 | QEMU_BUILD_BUG_MSG((CXL_BI_DECODER_REGISTERS_OFFSET + |
| 251 | CXL_BI_DECODER_REGISTERS_SIZE) >= 0x1000, |
| 252 | "No space for registers"); |
| 253 | |
| 254 | /* track BI explicit commit handling for route table and decoder */ |
| 255 | enum { |
| 256 | CXL_BISTATE_RT = 0, |
| 257 | CXL_BISTATE_DECODER, |
| 258 | CXL_BISTATE_MAX |
| 259 | }; |
| 260 | |
| 261 | typedef struct bi_state { |
| 262 | uint64_t last_commit; /* last 0->1 transition */ |
| 263 | } BIState; |
| 264 | |
| 265 | typedef struct component_registers { |
| 266 | /* |
| 267 | * Main memory region to be registered with QEMU core. |
| 268 | */ |
| 269 | MemoryRegion component_registers; |
| 270 | |
| 271 | /* |
| 272 | * CXL r3.1 Table 8-21: CXL Subsystem Component Register Ranges |
| 273 | * 0x0000 - 0x0fff CXL.io registers |
| 274 | * 0x1000 - 0x1fff CXL.cache and CXL.mem |
| 275 | * 0x2000 - 0xdfff Implementation specific |
| 276 | * 0xe000 - 0xe3ff CXL ARB/MUX registers |
| 277 | * 0xe400 - 0xffff RSVD |
| 278 | */ |
| 279 | uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; |
| 280 | MemoryRegion io; |
| 281 | |
| 282 | uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; |
| 283 | uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; |
| 284 | MemoryRegion cache_mem; |
| 285 | |
| 286 | MemoryRegion impl_specific; |
| 287 | MemoryRegion arb_mux; |
| 288 | MemoryRegion rsvd; |
| 289 | |
| 290 | /* special_ops is used for any component that needs any specific handling */ |
| 291 | MemoryRegionOps *special_ops; |
| 292 | } ComponentRegisters; |
| 293 | |
| 294 | /* |
| 295 | * A CXL component represents all entities in a CXL hierarchy. This includes, |
| 296 | * host bridges, root ports, upstream/downstream switch ports, and devices |
| 297 | */ |
| 298 | typedef struct cxl_component { |
| 299 | ComponentRegisters crb; |
| 300 | union { |
| 301 | struct { |
| 302 | Range dvsecs[CXL20_MAX_DVSEC]; |
| 303 | uint16_t dvsec_offset; |
| 304 | struct PCIDevice *pdev; |
| 305 | }; |
| 306 | }; |
| 307 | |
| 308 | CDATObject cdat; |
| 309 | BIState bi_state[CXL_BISTATE_MAX]; |
| 310 | } CXLComponentState; |
| 311 | |
| 312 | void cxl_component_register_block_init(Object *obj, |
| 313 | CXLComponentState *cxl_cstate, |
| 314 | const char *type); |
| 315 | void cxl_component_register_init_common(uint32_t *reg_state, |
| 316 | uint32_t *write_msk, |
| 317 | enum reg_type type, bool bi); |
| 318 | |
| 319 | void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, |
| 320 | enum reg_type cxl_dev_type, uint16_t length, |
| 321 | uint16_t type, uint8_t rev, uint8_t *body); |
| 322 | |
| 323 | int cxl_decoder_count_enc(int count); |
| 324 | int cxl_decoder_count_dec(int enc_cnt); |
| 325 | |
| 326 | uint8_t cxl_interleave_ways_enc(int iw, Error **errp); |
| 327 | int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp); |
| 328 | uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); |
| 329 | |
| 330 | hwaddr cxl_decode_ig(int ig); |
| 331 | |
| 332 | CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); |
| 333 | bool cxl_get_hb_passthrough(PCIHostState *hb); |
| 334 | |
| 335 | bool cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp); |
| 336 | void cxl_doe_cdat_release(CXLComponentState *cxl_cstate); |
| 337 | void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp); |
| 338 | |
| 339 | #endif |