| 1 | /* |
| 2 | * QEMU CXL Devices |
| 3 | * |
| 4 | * Copyright (c) 2020 Intel |
| 5 | * |
| 6 | * This work is licensed under the terms of the GNU GPL, version 2. See the |
| 7 | * COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef CXL_DEVICE_H |
| 11 | #define CXL_DEVICE_H |
| 12 | |
| 13 | #include "hw/cxl/cxl_component.h" |
| 14 | #include "hw/pci/pci_device.h" |
| 15 | #include "hw/core/register.h" |
| 16 | #include "hw/cxl/cxl_events.h" |
| 17 | |
| 18 | /* |
| 19 | * The following is how a CXL device's Memory Device registers are laid out. |
| 20 | * The only requirement from the spec is that the capabilities array and the |
| 21 | * capability headers start at offset 0 and are contiguously packed. The headers |
| 22 | * themselves provide offsets to the register fields. For this emulation, the |
| 23 | * actual registers * will start at offset 0x80 (m == 0x80). No secondary |
| 24 | * mailbox is implemented which means that the offset of the start of the |
| 25 | * mailbox payload (n) is given by |
| 26 | * n = m + sizeof(mailbox registers) + sizeof(device registers). |
| 27 | * |
| 28 | * +---------------------------------+ |
| 29 | * | | |
| 30 | * | Memory Device Registers | |
| 31 | * | | |
| 32 | * n + PAYLOAD_SIZE_MAX ----------------------------------- |
| 33 | * ^ | | |
| 34 | * | | | |
| 35 | * | | | |
| 36 | * | | | |
| 37 | * | | | |
| 38 | * | | Mailbox Payload | |
| 39 | * | | | |
| 40 | * | | | |
| 41 | * | | | |
| 42 | * n ----------------------------------- |
| 43 | * ^ | Mailbox Registers | |
| 44 | * | | | |
| 45 | * | ----------------------------------- |
| 46 | * | | | |
| 47 | * | | Device Registers | |
| 48 | * | | | |
| 49 | * m ----------------------------------> |
| 50 | * ^ | Memory Device Capability Header| |
| 51 | * | ----------------------------------- |
| 52 | * | | Mailbox Capability Header | |
| 53 | * | ----------------------------------- |
| 54 | * | | Device Capability Header | |
| 55 | * | ----------------------------------- |
| 56 | * | | Device Cap Array Register | |
| 57 | * 0 +---------------------------------+ |
| 58 | * |
| 59 | */ |
| 60 | |
| 61 | /* CXL r3.1 Figure 8-12: CXL Device Registers */ |
| 62 | #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 |
| 63 | /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */ |
| 64 | #define CXL_DEVICE_CAP_REG_SIZE 0x10 |
| 65 | |
| 66 | /* |
| 67 | * CXL r3.1 Section 8.2.8.2.1: CXL Device Capabilities + |
| 68 | * CXL r3.1 Section 8.2.8.5: Memory Device Capabilities |
| 69 | */ |
| 70 | #define CXL_DEVICE_CAPS_MAX 4 |
| 71 | #define CXL_CAPS_SIZE \ |
| 72 | (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */ |
| 73 | |
| 74 | #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */ |
| 75 | /* |
| 76 | * CXL r3.1 Section 8.2.8.3: Device Status Registers |
| 77 | * As it is the only Device Status Register in CXL r3.1 |
| 78 | */ |
| 79 | #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 |
| 80 | |
| 81 | #define CXL_MAILBOX_REGISTERS_OFFSET \ |
| 82 | (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH) |
| 83 | /* CXL r3.1 Figure 8-13: Mailbox Registers */ |
| 84 | #define CXL_MAILBOX_REGISTERS_SIZE 0x20 |
| 85 | #define CXL_MAILBOX_PAYLOAD_SHIFT 11 |
| 86 | #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) |
| 87 | #define CXL_MAILBOX_REGISTERS_LENGTH \ |
| 88 | (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) |
| 89 | |
| 90 | #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \ |
| 91 | (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH) |
| 92 | #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8 |
| 93 | |
| 94 | #define CXL_MMIO_SIZE \ |
| 95 | (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \ |
| 96 | CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH) |
| 97 | |
| 98 | /* CXL r3.1 Table 8-34: Command Return Codes */ |
| 99 | typedef enum { |
| 100 | CXL_MBOX_SUCCESS = 0x0, |
| 101 | CXL_MBOX_BG_STARTED = 0x1, |
| 102 | CXL_MBOX_INVALID_INPUT = 0x2, |
| 103 | CXL_MBOX_UNSUPPORTED = 0x3, |
| 104 | CXL_MBOX_INTERNAL_ERROR = 0x4, |
| 105 | CXL_MBOX_RETRY_REQUIRED = 0x5, |
| 106 | CXL_MBOX_BUSY = 0x6, |
| 107 | CXL_MBOX_MEDIA_DISABLED = 0x7, |
| 108 | CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8, |
| 109 | CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9, |
| 110 | CXL_MBOX_FW_AUTH_FAILED = 0xa, |
| 111 | CXL_MBOX_FW_INVALID_SLOT = 0xb, |
| 112 | CXL_MBOX_FW_ROLLEDBACK = 0xc, |
| 113 | CXL_MBOX_FW_REST_REQD = 0xd, |
| 114 | CXL_MBOX_INVALID_HANDLE = 0xe, |
| 115 | CXL_MBOX_INVALID_PA = 0xf, |
| 116 | CXL_MBOX_INJECT_POISON_LIMIT = 0x10, |
| 117 | CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11, |
| 118 | CXL_MBOX_ABORTED = 0x12, |
| 119 | CXL_MBOX_INVALID_SECURITY_STATE = 0x13, |
| 120 | CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, |
| 121 | CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, |
| 122 | CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, |
| 123 | CXL_MBOX_INVALID_LOG = 0x17, |
| 124 | CXL_MBOX_INTERRUPTED = 0x18, |
| 125 | CXL_MBOX_UNSUPPORTED_FEATURE_VERSION = 0x19, |
| 126 | CXL_MBOX_UNSUPPORTED_FEATURE_SELECTION_VALUE = 0x1a, |
| 127 | CXL_MBOX_FEATURE_TRANSFER_IN_PROGRESS = 0x1b, |
| 128 | CXL_MBOX_FEATURE_TRANSFER_OUT_OF_ORDER = 0x1c, |
| 129 | CXL_MBOX_RESOURCES_EXHAUSTED = 0x1d, |
| 130 | CXL_MBOX_INVALID_EXTENT_LIST = 0x1e, |
| 131 | CXL_MBOX_TRANSFER_OUT_OF_ORDER = 0x1f, |
| 132 | CXL_MBOX_REQUEST_ABORT_NOTSUP = 0x20, |
| 133 | CXL_MBOX_MAX = 0x20 |
| 134 | } CXLRetCode; |
| 135 | |
| 136 | /* r3.2 Section 7.6.7.6.2: Table 7-66: DSMAS Flags Bits */ |
| 137 | typedef enum { |
| 138 | CXL_DSMAS_FLAGS_NONVOLATILE = 2, |
| 139 | CXL_DSMAS_FLAGS_SHARABLE = 3, |
| 140 | CXL_DSMAS_FLAGS_HW_MANAGED_COHERENCY = 4, |
| 141 | CXL_DSMAS_FLAGS_IC_SPECIFIC_DC_MANAGEMENT = 5, |
| 142 | CXL_DSMAS_FLAGS_RDONLY = 6, |
| 143 | } CXLDSMASFlags; |
| 144 | |
| 145 | typedef struct CXLCCI CXLCCI; |
| 146 | typedef struct cxl_device_state CXLDeviceState; |
| 147 | struct cxl_cmd; |
| 148 | typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd, |
| 149 | uint8_t *payload_in, size_t len_in, |
| 150 | uint8_t *payload_out, size_t *len_out, |
| 151 | CXLCCI *cci); |
| 152 | struct cxl_cmd { |
| 153 | const char *name; |
| 154 | opcode_handler handler; |
| 155 | ssize_t in; |
| 156 | uint16_t effect; /* Reported in CEL */ |
| 157 | }; |
| 158 | |
| 159 | typedef struct CXLEvent { |
| 160 | CXLEventRecordRaw data; |
| 161 | QSIMPLEQ_ENTRY(CXLEvent) node; |
| 162 | } CXLEvent; |
| 163 | |
| 164 | typedef struct CXLEventLog { |
| 165 | uint16_t next_handle; |
| 166 | uint16_t overflow_err_count; |
| 167 | uint64_t first_overflow_timestamp; |
| 168 | uint64_t last_overflow_timestamp; |
| 169 | bool irq_enabled; |
| 170 | int irq_vec; |
| 171 | QemuMutex lock; |
| 172 | QSIMPLEQ_HEAD(, CXLEvent) events; |
| 173 | } CXLEventLog; |
| 174 | |
| 175 | typedef struct CXLCCI { |
| 176 | struct cxl_cmd cxl_cmd_set[256][256]; |
| 177 | struct cel_log { |
| 178 | uint16_t opcode; |
| 179 | uint16_t effect; |
| 180 | } cel_log[1 << 16]; |
| 181 | size_t cel_size; |
| 182 | |
| 183 | /* background command handling (times in ms) */ |
| 184 | struct { |
| 185 | uint16_t opcode; |
| 186 | uint16_t complete_pct; |
| 187 | uint16_t ret_code; /* Current value of retcode */ |
| 188 | bool aborted; |
| 189 | uint64_t starttime; |
| 190 | /* set by each bg cmd, cleared by the bg_timer when complete */ |
| 191 | uint64_t runtime; |
| 192 | QEMUTimer *timer; |
| 193 | QemuMutex lock; /* serializes mbox abort vs timer cb */ |
| 194 | } bg; |
| 195 | |
| 196 | /* firmware update */ |
| 197 | struct { |
| 198 | uint8_t active_slot; |
| 199 | uint8_t staged_slot; |
| 200 | bool slot[4]; |
| 201 | uint8_t curr_action; |
| 202 | uint8_t curr_slot; |
| 203 | /* handle partial transfers */ |
| 204 | bool transferring; |
| 205 | size_t prev_offset; |
| 206 | size_t prev_len; |
| 207 | time_t last_partxfer; |
| 208 | } fw; |
| 209 | |
| 210 | size_t payload_max; |
| 211 | /* Pointer to device hosting the CCI */ |
| 212 | DeviceState *d; |
| 213 | /* Pointer to the device hosting the protocol conversion */ |
| 214 | DeviceState *intf; |
| 215 | bool initialized; |
| 216 | } CXLCCI; |
| 217 | |
| 218 | typedef struct cxl_device_state { |
| 219 | MemoryRegion device_registers; |
| 220 | |
| 221 | /* CXL r3.1 Section 8.2.8.3: Device Status Registers */ |
| 222 | struct { |
| 223 | MemoryRegion device; |
| 224 | union { |
| 225 | uint8_t dev_reg_state[CXL_DEVICE_STATUS_REGISTERS_LENGTH]; |
| 226 | uint16_t dev_reg_state16[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 2]; |
| 227 | uint32_t dev_reg_state32[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 4]; |
| 228 | uint64_t dev_reg_state64[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 8]; |
| 229 | }; |
| 230 | uint64_t event_status; |
| 231 | }; |
| 232 | MemoryRegion memory_device; |
| 233 | struct { |
| 234 | MemoryRegion caps; |
| 235 | union { |
| 236 | uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; |
| 237 | uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8]; |
| 238 | }; |
| 239 | }; |
| 240 | |
| 241 | /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */ |
| 242 | struct { |
| 243 | MemoryRegion mailbox; |
| 244 | uint16_t payload_size; |
| 245 | uint8_t mbox_msi_n; |
| 246 | union { |
| 247 | uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH]; |
| 248 | uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2]; |
| 249 | uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4]; |
| 250 | uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8]; |
| 251 | }; |
| 252 | }; |
| 253 | |
| 254 | /* Stash the memory device status value */ |
| 255 | uint64_t memdev_status; |
| 256 | |
| 257 | struct { |
| 258 | bool set; |
| 259 | uint64_t last_set; |
| 260 | uint64_t host_set; |
| 261 | } timestamp; |
| 262 | |
| 263 | /* memory region size, HDM */ |
| 264 | uint64_t static_mem_size; |
| 265 | uint64_t pmem_size; |
| 266 | uint64_t vmem_size; |
| 267 | |
| 268 | const struct cxl_cmd (*cxl_cmd_set)[256]; |
| 269 | CXLEventLog event_logs[CXL_EVENT_TYPE_MAX]; |
| 270 | } CXLDeviceState; |
| 271 | |
| 272 | /* Initialize the register block for a device */ |
| 273 | void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev, |
| 274 | CXLCCI *cci); |
| 275 | |
| 276 | typedef struct CXLType3Dev CXLType3Dev; |
| 277 | typedef struct CSWMBCCIDev CSWMBCCIDev; |
| 278 | /* Set up default values for the register block */ |
| 279 | void cxl_device_register_init_t3(CXLType3Dev *ct3d, int msi_n); |
| 280 | void cxl_device_register_init_swcci(CSWMBCCIDev *sw, int msi_n); |
| 281 | |
| 282 | /* |
| 283 | * CXL r3.1 Section 8.2.8.1: CXL Device Capabilities Array Register |
| 284 | * Documented as a 128 bit register, but 64 bit accesses and the second |
| 285 | * 64 bits are currently reserved. |
| 286 | */ |
| 287 | REG64(CXL_DEV_CAP_ARRAY, 0) |
| 288 | FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) |
| 289 | FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) |
| 290 | FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16) |
| 291 | |
| 292 | void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type, |
| 293 | bool available); |
| 294 | |
| 295 | /* |
| 296 | * Helper macro to initialize capability headers for CXL devices. |
| 297 | * |
| 298 | * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is |
| 299 | * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register |
| 300 | * Interface, it says: |
| 301 | * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that |
| 302 | * > is the maximum access size allowed for these registers. If this rule is not |
| 303 | * > followed, the behavior is undefined. |
| 304 | * |
| 305 | * > To illustrate how the fields fit together, the layouts ... are shown as |
| 306 | * > wider than a 64 bit register. Implementations are expected to use any size |
| 307 | * > accesses for this information up to 64 bits without lost of functionality |
| 308 | * |
| 309 | * Here we've chosen to make it 4 dwords. |
| 310 | */ |
| 311 | #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ |
| 312 | REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ |
| 313 | FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ |
| 314 | FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ |
| 315 | REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ |
| 316 | FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ |
| 317 | REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ |
| 318 | FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) |
| 319 | |
| 320 | CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET) |
| 321 | CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ |
| 322 | CXL_DEVICE_CAP_REG_SIZE) |
| 323 | CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, |
| 324 | CXL_DEVICE_CAP_HDR1_OFFSET + |
| 325 | CXL_DEVICE_CAP_REG_SIZE * 2) |
| 326 | |
| 327 | void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max); |
| 328 | void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, |
| 329 | DeviceState *d, size_t payload_max); |
| 330 | void cxl_init_cci(CXLCCI *cci, size_t payload_max); |
| 331 | void cxl_destroy_cci(CXLCCI *cci); |
| 332 | void cxl_add_cci_commands(CXLCCI *cci, const struct cxl_cmd (*cxl_cmd_set)[256], |
| 333 | size_t payload_max); |
| 334 | int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd, |
| 335 | size_t len_in, uint8_t *pl_in, |
| 336 | size_t *len_out, uint8_t *pl_out, |
| 337 | bool *bg_started); |
| 338 | void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d, |
| 339 | DeviceState *intf, |
| 340 | size_t payload_max); |
| 341 | |
| 342 | void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d, |
| 343 | DeviceState *intf, size_t payload_max); |
| 344 | |
| 345 | #define cxl_device_cap_init(dstate, reg, cap_id, ver) \ |
| 346 | do { \ |
| 347 | uint32_t *cap_hdrs = dstate->caps_reg_state32; \ |
| 348 | int which = R_CXL_DEV_##reg##_CAP_HDR0; \ |
| 349 | cap_hdrs[which] = \ |
| 350 | FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \ |
| 351 | CAP_ID, cap_id); \ |
| 352 | cap_hdrs[which] = FIELD_DP32( \ |
| 353 | cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, ver); \ |
| 354 | cap_hdrs[which + 1] = \ |
| 355 | FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ |
| 356 | CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ |
| 357 | cap_hdrs[which + 2] = \ |
| 358 | FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ |
| 359 | CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ |
| 360 | } while (0) |
| 361 | |
| 362 | /* CXL r3.2 Section 8.2.8.3.1: Event Status Register */ |
| 363 | #define CXL_DEVICE_STATUS_VERSION 2 |
| 364 | REG64(CXL_DEV_EVENT_STATUS, 0) |
| 365 | FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32) |
| 366 | |
| 367 | #define CXL_DEV_MAILBOX_VERSION 1 |
| 368 | /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */ |
| 369 | REG32(CXL_DEV_MAILBOX_CAP, 0) |
| 370 | FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) |
| 371 | FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) |
| 372 | FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) |
| 373 | FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) |
| 374 | FIELD(CXL_DEV_MAILBOX_CAP, MBOX_READY_TIME, 11, 8) |
| 375 | FIELD(CXL_DEV_MAILBOX_CAP, TYPE, 19, 4) |
| 376 | |
| 377 | /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */ |
| 378 | REG32(CXL_DEV_MAILBOX_CTRL, 4) |
| 379 | FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) |
| 380 | FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) |
| 381 | FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) |
| 382 | |
| 383 | /* CXL r3.1 Section 8.2.8.4.5: Command Register */ |
| 384 | REG64(CXL_DEV_MAILBOX_CMD, 8) |
| 385 | FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8) |
| 386 | FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8) |
| 387 | FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20) |
| 388 | |
| 389 | /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */ |
| 390 | REG64(CXL_DEV_MAILBOX_STS, 0x10) |
| 391 | FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) |
| 392 | FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) |
| 393 | FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) |
| 394 | |
| 395 | /* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */ |
| 396 | REG64(CXL_DEV_BG_CMD_STS, 0x18) |
| 397 | FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16) |
| 398 | FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7) |
| 399 | FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16) |
| 400 | FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16) |
| 401 | |
| 402 | /* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */ |
| 403 | REG32(CXL_DEV_CMD_PAYLOAD, 0x20) |
| 404 | |
| 405 | /* CXL r3.1 Section 8.2.8.4.1: Memory Device Status Registers */ |
| 406 | #define CXL_MEM_DEV_STATUS_VERSION 1 |
| 407 | REG64(CXL_MEM_DEV_STS, 0) |
| 408 | FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1) |
| 409 | FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1) |
| 410 | FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2) |
| 411 | FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) |
| 412 | FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) |
| 413 | |
| 414 | static inline void __toggle_media(CXLDeviceState *cxl_dstate, int val) |
| 415 | { |
| 416 | uint64_t dev_status_reg; |
| 417 | |
| 418 | dev_status_reg = cxl_dstate->memdev_status; |
| 419 | dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS, |
| 420 | val); |
| 421 | cxl_dstate->memdev_status = dev_status_reg; |
| 422 | } |
| 423 | #define cxl_dev_disable_media(cxlds) \ |
| 424 | do { __toggle_media((cxlds), 0x3); } while (0) |
| 425 | #define cxl_dev_enable_media(cxlds) \ |
| 426 | do { __toggle_media((cxlds), 0x1); } while (0) |
| 427 | |
| 428 | static inline bool cxl_dev_media_disabled(CXLDeviceState *cxl_dstate) |
| 429 | { |
| 430 | uint64_t dev_status_reg = cxl_dstate->mbox_reg_state64[R_CXL_MEM_DEV_STS]; |
| 431 | return FIELD_EX64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS) == 0x3; |
| 432 | } |
| 433 | |
| 434 | static inline bool maintenance_running(CXLCCI *cci) |
| 435 | { |
| 436 | return cci->bg.runtime && cci->bg.opcode == 0x0600; |
| 437 | } |
| 438 | |
| 439 | static inline bool scan_media_running(CXLCCI *cci) |
| 440 | { |
| 441 | return !!cci->bg.runtime && cci->bg.opcode == 0x4304; |
| 442 | } |
| 443 | |
| 444 | typedef struct CXLError { |
| 445 | QTAILQ_ENTRY(CXLError) node; |
| 446 | int type; /* Error code as per FE definition */ |
| 447 | uint32_t header[CXL_RAS_ERR_HEADER_NUM]; |
| 448 | } CXLError; |
| 449 | |
| 450 | typedef QTAILQ_HEAD(, CXLError) CXLErrorList; |
| 451 | |
| 452 | typedef struct CXLMaintenance { |
| 453 | uint64_t dpa; |
| 454 | uint16_t validity_flags; |
| 455 | uint8_t channel; |
| 456 | uint8_t rank; |
| 457 | uint32_t nibble_mask; |
| 458 | uint8_t bank_group; |
| 459 | uint8_t bank; |
| 460 | uint32_t row; |
| 461 | uint16_t column; |
| 462 | uint8_t component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE]; |
| 463 | uint8_t sub_channel; |
| 464 | QLIST_ENTRY(CXLMaintenance) node; |
| 465 | } CXLMaintenance; |
| 466 | |
| 467 | typedef QLIST_HEAD(, CXLMaintenance) CXLMaintenanceList; |
| 468 | |
| 469 | typedef struct CXLPoison { |
| 470 | uint64_t start, length; |
| 471 | uint8_t type; |
| 472 | #define CXL_POISON_TYPE_EXTERNAL 0x1 |
| 473 | #define CXL_POISON_TYPE_INTERNAL 0x2 |
| 474 | #define CXL_POISON_TYPE_INJECTED 0x3 |
| 475 | QLIST_ENTRY(CXLPoison) node; |
| 476 | } CXLPoison; |
| 477 | |
| 478 | typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; |
| 479 | #define CXL_POISON_LIST_LIMIT 256 |
| 480 | |
| 481 | /* CXL memory maintenance operation */ |
| 482 | /* |
| 483 | * CXL r3.2 section 8.2.10.7.2, Table 8-125: Mainteance Operation: |
| 484 | * Classes, Subclasses, and Feature UUIDs |
| 485 | */ |
| 486 | #define CXL_MEMDEV_MAINT_CLASS_NO_OP 0x0 |
| 487 | #define CXL_MEMDEV_MAINT_CLASS_PPR 0x1 |
| 488 | #define CXL_MEMDEV_MAINT_CLASS_SPARING 0x2 |
| 489 | #define CXL_MEMDEV_MAINT_CLASS_DEV_BUILT_IN_TEST 0x3 |
| 490 | |
| 491 | #define CXL_MEMDEV_MAINT_SUBCLASS_SPPR 0x0 |
| 492 | #define CXL_MEMDEV_MAINT_SUBCLASS_HPPR 0x1 |
| 493 | |
| 494 | #define CXL_MEMDEV_MAINT_SUBCLASS_CACHELINE_SPARING 0x0 |
| 495 | #define CXL_MEMDEV_MAINT_SUBCLASS_ROW_SPARING 0x1 |
| 496 | #define CXL_MEMDEV_MAINT_SUBCLASS_BANK_SPARING 0x2 |
| 497 | #define CXL_MEMDEV_MAINT_SUBCLASS_RANK_SPARING 0x3 |
| 498 | |
| 499 | /* CXL memory Post Package Repair control attributes */ |
| 500 | /* |
| 501 | * CXL r3.2 section 8.2.10.7.2.1, Table 8-128 and 8-129: |
| 502 | * sPPR Feature Readable/Writable Attributes |
| 503 | */ |
| 504 | typedef struct CXLMemSoftPPRReadAttrs { |
| 505 | uint8_t max_maint_latency; |
| 506 | uint16_t op_caps; |
| 507 | uint16_t op_mode; |
| 508 | uint8_t maint_op_class; |
| 509 | uint8_t maint_op_subclass; |
| 510 | uint8_t rsvd[9]; |
| 511 | uint8_t sppr_flags; |
| 512 | uint16_t restriction_flags; |
| 513 | uint8_t sppr_op_mode; |
| 514 | } QEMU_PACKED CXLMemSoftPPRReadAttrs; |
| 515 | |
| 516 | typedef struct CXLMemSoftPPRWriteAttrs { |
| 517 | uint16_t op_mode; |
| 518 | uint8_t sppr_op_mode; |
| 519 | } QEMU_PACKED CXLMemSoftPPRWriteAttrs; |
| 520 | |
| 521 | #define CXL_MEMDEV_SPPR_GET_FEATURE_VERSION 0x03 |
| 522 | #define CXL_MEMDEV_SPPR_SET_FEATURE_VERSION 0x03 |
| 523 | #define CXL_MEMDEV_SPPR_DPA_SUPPORT_FLAG BIT(0) |
| 524 | #define CXL_MEMDEV_SPPR_NIBBLE_SUPPORT_FLAG BIT(1) |
| 525 | #define CXL_MEMDEV_SPPR_MEM_SPARING_EV_REC_CAP_FLAG BIT(2) |
| 526 | #define CXL_MEMDEV_SPPR_DEV_INITIATED_AT_BOOT_CAP_FLAG BIT(3) |
| 527 | |
| 528 | #define CXL_MEMDEV_SPPR_OP_MODE_MEM_SPARING_EV_REC_EN BIT(0) |
| 529 | #define CXL_MEMDEV_SPPR_OP_MODE_DEV_INITIATED_AT_BOOT BIT(1) |
| 530 | |
| 531 | /* |
| 532 | * CXL r3.2 section 8.2.10.7.2.2, Table 8-131 and 8-132: |
| 533 | * hPPR Feature Readable/Writable Attributes |
| 534 | */ |
| 535 | typedef struct CXLMemHardPPRReadAttrs { |
| 536 | uint8_t max_maint_latency; |
| 537 | uint16_t op_caps; |
| 538 | uint16_t op_mode; |
| 539 | uint8_t maint_op_class; |
| 540 | uint8_t maint_op_subclass; |
| 541 | uint8_t rsvd[9]; |
| 542 | uint8_t hppr_flags; |
| 543 | uint16_t restriction_flags; |
| 544 | uint8_t hppr_op_mode; |
| 545 | } QEMU_PACKED CXLMemHardPPRReadAttrs; |
| 546 | |
| 547 | typedef struct CXLMemHardPPRWriteAttrs { |
| 548 | uint16_t op_mode; |
| 549 | uint8_t hppr_op_mode; |
| 550 | } QEMU_PACKED CXLMemHardPPRWriteAttrs; |
| 551 | |
| 552 | #define CXL_MEMDEV_HPPR_GET_FEATURE_VERSION 0x03 |
| 553 | #define CXL_MEMDEV_HPPR_SET_FEATURE_VERSION 0x03 |
| 554 | #define CXL_MEMDEV_HPPR_DPA_SUPPORT_FLAG BIT(0) |
| 555 | #define CXL_MEMDEV_HPPR_NIBBLE_SUPPORT_FLAG BIT(1) |
| 556 | #define CXL_MEMDEV_HPPR_MEM_SPARING_EV_REC_CAP_FLAG BIT(2) |
| 557 | #define CXL_MEMDEV_HPPR_DEV_INITIATED_AT_BOOT_CAP_FLAG BIT(3) |
| 558 | |
| 559 | #define CXL_MEMDEV_HPPR_OP_MODE_MEM_SPARING_EV_REC_EN BIT(0) |
| 560 | #define CXL_MEMDEV_HPPR_OP_MODE_DEV_INITIATED_AT_BOOT BIT(1) |
| 561 | |
| 562 | /* CXL memory device patrol scrub control attributes */ |
| 563 | typedef struct CXLMemPatrolScrubReadAttrs { |
| 564 | uint8_t scrub_cycle_cap; |
| 565 | uint16_t scrub_cycle; |
| 566 | uint8_t scrub_flags; |
| 567 | } QEMU_PACKED CXLMemPatrolScrubReadAttrs; |
| 568 | |
| 569 | typedef struct CXLMemPatrolScrubWriteAttrs { |
| 570 | uint8_t scrub_cycle_hr; |
| 571 | uint8_t scrub_flags; |
| 572 | } QEMU_PACKED CXLMemPatrolScrubWriteAttrs; |
| 573 | |
| 574 | #define CXL_MEMDEV_PS_GET_FEATURE_VERSION 0x01 |
| 575 | #define CXL_MEMDEV_PS_SET_FEATURE_VERSION 0x01 |
| 576 | #define CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT BIT(0) |
| 577 | #define CXL_MEMDEV_PS_SCRUB_REALTIME_REPORT_CAP_DEFAULT BIT(1) |
| 578 | #define CXL_MEMDEV_PS_CUR_SCRUB_CYCLE_DEFAULT 12 |
| 579 | #define CXL_MEMDEV_PS_MIN_SCRUB_CYCLE_DEFAULT 1 |
| 580 | #define CXL_MEMDEV_PS_ENABLE_DEFAULT 0 |
| 581 | |
| 582 | /* CXL memory device DDR5 ECS control attributes */ |
| 583 | #define CXL_ECS_GET_FEATURE_VERSION 0x01 |
| 584 | #define CXL_ECS_SET_FEATURE_VERSION 0x01 |
| 585 | #define CXL_ECS_LOG_ENTRY_TYPE_DEFAULT 0x01 |
| 586 | #define CXL_ECS_REALTIME_REPORT_CAP_DEFAULT 1 |
| 587 | #define CXL_ECS_THRESHOLD_COUNT_DEFAULT 3 /* 3: 256, 4: 1024, 5: 4096 */ |
| 588 | #define CXL_ECS_MODE_DEFAULT 0 |
| 589 | #define CXL_ECS_NUM_MEDIA_FRUS 3 /* Default */ |
| 590 | |
| 591 | typedef struct CXLMemECSFRUReadAttrs { |
| 592 | uint8_t ecs_cap; |
| 593 | uint16_t ecs_config; |
| 594 | uint8_t ecs_flags; |
| 595 | } QEMU_PACKED CXLMemECSFRUReadAttrs; |
| 596 | |
| 597 | typedef struct CXLMemECSReadAttrs { |
| 598 | uint8_t ecs_log_cap; |
| 599 | CXLMemECSFRUReadAttrs fru_attrs[CXL_ECS_NUM_MEDIA_FRUS]; |
| 600 | } QEMU_PACKED CXLMemECSReadAttrs; |
| 601 | |
| 602 | typedef struct CXLMemECSFRUWriteAttrs { |
| 603 | uint16_t ecs_config; |
| 604 | } QEMU_PACKED CXLMemECSFRUWriteAttrs; |
| 605 | |
| 606 | typedef struct CXLMemECSWriteAttrs { |
| 607 | uint8_t ecs_log_cap; |
| 608 | CXLMemECSFRUWriteAttrs fru_attrs[CXL_ECS_NUM_MEDIA_FRUS]; |
| 609 | } QEMU_PACKED CXLMemECSWriteAttrs; |
| 610 | |
| 611 | /* |
| 612 | * CXL r3.2 section 8.2.10.7.2.3, Table 8-134 and 8-135: |
| 613 | * Memory Sparing Feature Readable/Writable Attributes |
| 614 | */ |
| 615 | typedef struct CXLMemSparingReadAttrs { |
| 616 | uint8_t max_maint_latency; |
| 617 | uint16_t op_caps; |
| 618 | uint16_t op_mode; |
| 619 | uint8_t maint_op_class; |
| 620 | uint8_t maint_op_subclass; |
| 621 | uint8_t rsvd[10]; |
| 622 | uint16_t restriction_flags; |
| 623 | } QEMU_PACKED CXLMemSparingReadAttrs; |
| 624 | |
| 625 | typedef struct CXLMemSparingWriteAttrs { |
| 626 | uint16_t op_mode; |
| 627 | } QEMU_PACKED CXLMemSparingWriteAttrs; |
| 628 | |
| 629 | #define CXL_MEMDEV_SPARING_GET_FEATURE_VERSION 0x01 |
| 630 | #define CXL_MEMDEV_SPARING_SET_FEATURE_VERSION 0x01 |
| 631 | #define CXL_MEMDEV_SPARING_SAFE_IN_USE_FLAG BIT(0) |
| 632 | #define CXL_MEMDEV_HARD_SPARING_SUPPORT_FLAG BIT(1) |
| 633 | #define CXL_MEMDEV_SOFT_SPARING_SUPPORT_FLAG BIT(2) |
| 634 | |
| 635 | #define DCD_MAX_NUM_REGION 8 |
| 636 | |
| 637 | typedef struct CXLDCExtentRaw { |
| 638 | uint64_t start_dpa; |
| 639 | uint64_t len; |
| 640 | uint8_t tag[0x10]; |
| 641 | uint16_t shared_seq; |
| 642 | uint8_t rsvd[0x6]; |
| 643 | } QEMU_PACKED CXLDCExtentRaw; |
| 644 | |
| 645 | typedef struct CXLDCExtent { |
| 646 | uint64_t start_dpa; |
| 647 | uint64_t len; |
| 648 | uint8_t tag[0x10]; |
| 649 | uint16_t shared_seq; |
| 650 | uint8_t rsvd[0x6]; |
| 651 | |
| 652 | QTAILQ_ENTRY(CXLDCExtent) node; |
| 653 | } CXLDCExtent; |
| 654 | typedef QTAILQ_HEAD(, CXLDCExtent) CXLDCExtentList; |
| 655 | |
| 656 | typedef struct CXLDCExtentGroup { |
| 657 | CXLDCExtentList list; |
| 658 | QTAILQ_ENTRY(CXLDCExtentGroup) node; |
| 659 | } CXLDCExtentGroup; |
| 660 | typedef QTAILQ_HEAD(, CXLDCExtentGroup) CXLDCExtentGroupList; |
| 661 | |
| 662 | typedef struct CXLDCRegion { |
| 663 | uint64_t base; /* aligned to 256*MiB */ |
| 664 | uint64_t decode_len; /* aligned to 256*MiB */ |
| 665 | uint64_t len; |
| 666 | uint64_t block_size; |
| 667 | uint32_t dsmadhandle; |
| 668 | uint8_t flags; |
| 669 | unsigned long *blk_bitmap; |
| 670 | uint64_t supported_blk_size_bitmask; |
| 671 | QemuMutex bitmap_lock; |
| 672 | /* Following bools make up dsmas flags, as defined in the CDAT */ |
| 673 | bool nonvolatile; |
| 674 | bool sharable; |
| 675 | bool hw_managed_coherency; |
| 676 | bool ic_specific_dc_management; |
| 677 | bool rdonly; |
| 678 | } CXLDCRegion; |
| 679 | |
| 680 | typedef struct CXLSetFeatureInfo { |
| 681 | QemuUUID uuid; |
| 682 | uint8_t data_transfer_flag; |
| 683 | bool data_saved_across_reset; |
| 684 | uint16_t data_offset; |
| 685 | size_t data_size; |
| 686 | } CXLSetFeatureInfo; |
| 687 | |
| 688 | typedef struct CXLFixedWindow CXLFixedWindow; |
| 689 | |
| 690 | struct CXLSanitizeInfo; |
| 691 | |
| 692 | typedef struct CXLAlertConfig { |
| 693 | uint8_t valid_alerts; |
| 694 | uint8_t enable_alerts; |
| 695 | uint8_t life_used_crit_alert_thresh; |
| 696 | uint8_t life_used_warn_thresh; |
| 697 | uint16_t over_temp_crit_alert_thresh; |
| 698 | uint16_t under_temp_crit_alert_thresh; |
| 699 | uint16_t over_temp_warn_thresh; |
| 700 | uint16_t under_temp_warn_thresh; |
| 701 | uint16_t cor_vmem_err_warn_thresh; |
| 702 | uint16_t cor_pmem_err_warn_thresh; |
| 703 | } QEMU_PACKED CXLAlertConfig; |
| 704 | |
| 705 | struct CXLType3Dev { |
| 706 | /* Private */ |
| 707 | PCIDevice parent_obj; |
| 708 | |
| 709 | /* Properties */ |
| 710 | HostMemoryBackend *hostmem; /* deprecated */ |
| 711 | HostMemoryBackend *hostvmem; |
| 712 | HostMemoryBackend *hostpmem; |
| 713 | HostMemoryBackend *lsa; |
| 714 | uint64_t sn; |
| 715 | |
| 716 | /* State */ |
| 717 | MemoryRegion direct_mr[CXL_HDM_DECODER_COUNT]; |
| 718 | CXLFixedWindow *direct_mr_fw[CXL_HDM_DECODER_COUNT]; |
| 719 | AddressSpace hostvmem_as; |
| 720 | AddressSpace hostpmem_as; |
| 721 | CXLComponentState cxl_cstate; |
| 722 | CXLDeviceState cxl_dstate; |
| 723 | CXLCCI cci; /* Primary PCI mailbox CCI */ |
| 724 | /* Always initialized as no way to know if a VDM might show up */ |
| 725 | CXLCCI vdm_fm_owned_ld_mctp_cci; |
| 726 | CXLCCI ld0_cci; |
| 727 | |
| 728 | CXLAlertConfig alert_config; |
| 729 | |
| 730 | /* PCIe link characteristics */ |
| 731 | PCIExpLinkSpeed speed; |
| 732 | PCIExpLinkWidth width; |
| 733 | bool flitmode; |
| 734 | |
| 735 | /* DOE */ |
| 736 | DOECap doe_cdat; |
| 737 | |
| 738 | /* Error injection */ |
| 739 | CXLErrorList error_list; |
| 740 | |
| 741 | /* Keep track of maintenance requests */ |
| 742 | CXLMaintenanceList maint_list; |
| 743 | |
| 744 | /* Poison Injection - cache */ |
| 745 | CXLPoisonList poison_list; |
| 746 | unsigned int poison_list_cnt; |
| 747 | bool poison_list_overflowed; |
| 748 | uint64_t poison_list_overflow_ts; |
| 749 | /* Poison Injection - backup */ |
| 750 | CXLPoisonList poison_list_bkp; |
| 751 | CXLPoisonList scan_media_results; |
| 752 | bool scan_media_hasrun; |
| 753 | |
| 754 | CXLSetFeatureInfo set_feat_info; |
| 755 | |
| 756 | /* PPR control attributes */ |
| 757 | CXLMemSoftPPRReadAttrs soft_ppr_attrs; |
| 758 | CXLMemSoftPPRWriteAttrs soft_ppr_wr_attrs; |
| 759 | CXLMemHardPPRReadAttrs hard_ppr_attrs; |
| 760 | CXLMemHardPPRWriteAttrs hard_ppr_wr_attrs; |
| 761 | /* Patrol scrub control attributes */ |
| 762 | CXLMemPatrolScrubReadAttrs patrol_scrub_attrs; |
| 763 | CXLMemPatrolScrubWriteAttrs patrol_scrub_wr_attrs; |
| 764 | /* ECS control attributes */ |
| 765 | CXLMemECSReadAttrs ecs_attrs; |
| 766 | CXLMemECSWriteAttrs ecs_wr_attrs; |
| 767 | /* Memory Sparing control attributes */ |
| 768 | CXLMemSparingReadAttrs cacheline_sparing_attrs; |
| 769 | CXLMemSparingWriteAttrs cacheline_sparing_wr_attrs; |
| 770 | CXLMemSparingReadAttrs row_sparing_attrs; |
| 771 | CXLMemSparingWriteAttrs row_sparing_wr_attrs; |
| 772 | CXLMemSparingReadAttrs bank_sparing_attrs; |
| 773 | CXLMemSparingWriteAttrs bank_sparing_wr_attrs; |
| 774 | CXLMemSparingReadAttrs rank_sparing_attrs; |
| 775 | CXLMemSparingWriteAttrs rank_sparing_wr_attrs; |
| 776 | |
| 777 | /* BI flows */ |
| 778 | bool hdmdb; |
| 779 | |
| 780 | struct dynamic_capacity { |
| 781 | HostMemoryBackend *host_dc; |
| 782 | AddressSpace host_dc_as; |
| 783 | /* |
| 784 | * total_capacity is equivalent to the dynamic capability |
| 785 | * memory region size. |
| 786 | */ |
| 787 | uint64_t total_capacity; /* 256M aligned */ |
| 788 | CXLDCExtentList extents; |
| 789 | CXLDCExtentGroupList extents_pending; |
| 790 | uint32_t total_extent_count; |
| 791 | uint32_t nr_extents_accepted; |
| 792 | uint32_t ext_list_gen_seq; |
| 793 | |
| 794 | uint8_t num_regions; /* 0-8 regions */ |
| 795 | CXLDCRegion regions[DCD_MAX_NUM_REGION]; |
| 796 | } dc; |
| 797 | |
| 798 | struct CXLSanitizeInfo *media_op_sanitize; |
| 799 | }; |
| 800 | |
| 801 | #define TYPE_CXL_TYPE3 "cxl-type3" |
| 802 | OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3) |
| 803 | |
| 804 | struct CXLType3Class { |
| 805 | /* Private */ |
| 806 | PCIDeviceClass parent_class; |
| 807 | |
| 808 | /* public */ |
| 809 | uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); |
| 810 | |
| 811 | uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size, |
| 812 | uint64_t offset); |
| 813 | void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size, |
| 814 | uint64_t offset); |
| 815 | bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset, |
| 816 | uint8_t *data); |
| 817 | }; |
| 818 | |
| 819 | struct CSWMBCCIDev { |
| 820 | PCIDevice parent_obj; |
| 821 | PCIDevice *target; |
| 822 | CXLComponentState cxl_cstate; |
| 823 | CXLDeviceState cxl_dstate; |
| 824 | CXLCCI *cci; |
| 825 | }; |
| 826 | |
| 827 | #define TYPE_CXL_SWITCH_MAILBOX_CCI "cxl-switch-mailbox-cci" |
| 828 | OBJECT_DECLARE_TYPE(CSWMBCCIDev, CSWMBCCIClass, CXL_SWITCH_MAILBOX_CCI) |
| 829 | |
| 830 | MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, |
| 831 | unsigned size, MemTxAttrs attrs); |
| 832 | MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, |
| 833 | unsigned size, MemTxAttrs attrs); |
| 834 | |
| 835 | uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds); |
| 836 | |
| 837 | void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num); |
| 838 | bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogType log_type, |
| 839 | CXLEventRecordRaw *event); |
| 840 | CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl, |
| 841 | uint8_t log_type, int max_recs, |
| 842 | size_t *len); |
| 843 | CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds, |
| 844 | CXLClearEventPayload *pl); |
| 845 | void cxl_discard_all_event_records(CXLDeviceState *cxlds); |
| 846 | |
| 847 | void cxl_event_irq_assert(CXLType3Dev *ct3d); |
| 848 | |
| 849 | void cxl_set_poison_list_overflowed(CXLType3Dev *ct3d); |
| 850 | void cxl_clear_poison_list_overflowed(CXLType3Dev *ct3d); |
| 851 | |
| 852 | CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len); |
| 853 | |
| 854 | void cxl_remove_extent_from_extent_list(CXLDCExtentList *list, |
| 855 | CXLDCExtent *extent); |
| 856 | void cxl_insert_extent_to_extent_list(CXLDCExtentList *list, uint64_t dpa, |
| 857 | uint64_t len, uint8_t *tag, |
| 858 | uint16_t shared_seq); |
| 859 | bool test_any_bits_set(const unsigned long *addr, unsigned long nr, |
| 860 | unsigned long size); |
| 861 | bool cxl_extents_contains_dpa_range(CXLDCExtentList *list, |
| 862 | uint64_t dpa, uint64_t len); |
| 863 | CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group, |
| 864 | uint64_t dpa, |
| 865 | uint64_t len, |
| 866 | uint8_t *tag, |
| 867 | uint16_t shared_seq); |
| 868 | void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list, |
| 869 | CXLDCExtentGroup *group); |
| 870 | uint32_t cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list); |
| 871 | void ct3_set_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, |
| 872 | uint64_t len); |
| 873 | void ct3_clear_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, |
| 874 | uint64_t len); |
| 875 | bool ct3_test_region_block_backed(CXLType3Dev *ct3d, uint64_t dpa, |
| 876 | uint64_t len); |
| 877 | void cxl_assign_event_header(CXLEventRecordHdr *hdr, |
| 878 | const QemuUUID *uuid, uint32_t flags, |
| 879 | uint8_t length, uint64_t timestamp, |
| 880 | bool has_maint_op_class, uint8_t maint_op_class, |
| 881 | bool has_maint_op_subclass, |
| 882 | uint8_t maint_op_subclass, |
| 883 | bool has_ld_id, uint16_t ld_id, |
| 884 | bool has_head_id, uint8_t head_id); |
| 885 | void cxl_create_dc_event_records_for_extents(CXLType3Dev *ct3d, |
| 886 | CXLDCEventType type, |
| 887 | CXLDCExtentRaw extents[], |
| 888 | uint32_t ext_count); |
| 889 | bool cxl_extents_overlaps_dpa_range(CXLDCExtentList *list, |
| 890 | uint64_t dpa, uint64_t len); |
| 891 | bool cxl_extent_groups_overlaps_dpa_range(CXLDCExtentGroupList *list, |
| 892 | uint64_t dpa, uint64_t len); |
| 893 | #endif |