| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #ifndef CXL_PORT_H |
| 4 | #define CXL_PORT_H |
| 5 | |
| 6 | #include "qemu/thread.h" |
| 7 | |
| 8 | /* CXL r3.2 Table 7-19: Get Physical Port State Port Information Block Format */ |
| 9 | #define CXL_PORT_CONFIG_STATE_DISABLED 0x0 |
| 10 | #define CXL_PORT_CONFIG_STATE_BIND_IN_PROGRESS 0x1 |
| 11 | #define CXL_PORT_CONFIG_STATE_UNBIND_IN_PROGRESS 0x2 |
| 12 | #define CXL_PORT_CONFIG_STATE_DSP 0x3 |
| 13 | #define CXL_PORT_CONFIG_STATE_USP 0x4 |
| 14 | #define CXL_PORT_CONFIG_STATE_FABRIC_PORT 0x5 |
| 15 | #define CXL_PORT_CONFIG_STATE_INVALID_PORT_ID 0xF |
| 16 | |
| 17 | #define CXL_PORT_CONNECTED_DEV_MODE_NOT_CXL_OR_DISCONN 0x00 |
| 18 | #define CXL_PORT_CONNECTED_DEV_MODE_RCD 0x01 |
| 19 | #define CXL_PORT_CONNECTED_DEV_MODE_68B_VH 0x02 |
| 20 | #define CXL_PORT_CONNECTED_DEV_MODE_256B 0x03 |
| 21 | #define CXL_PORT_CONNECTED_DEV_MODE_LO_256B 0x04 |
| 22 | #define CXL_PORT_CONNECTED_DEV_MODE_PBR 0x05 |
| 23 | |
| 24 | #define CXL_PORT_CONNECTED_DEV_TYPE_NONE 0x00 |
| 25 | #define CXL_PORT_CONNECTED_DEV_TYPE_PCIE 0x01 |
| 26 | #define CXL_PORT_CONNECTED_DEV_TYPE_1 0x02 |
| 27 | #define CXL_PORT_CONNECTED_DEV_TYPE_2_OR_HBR_SWITCH 0x03 |
| 28 | #define CXL_PORT_CONNECTED_DEV_TYPE_3_SLD 0x04 |
| 29 | #define CXL_PORT_CONNECTED_DEV_TYPE_3_MLD 0x05 |
| 30 | #define CXL_PORT_CONNECTED_DEV_PBR_COMPONENT 0x06 |
| 31 | |
| 32 | #define CXL_PORT_SUPPORTS_RCD BIT(0) |
| 33 | #define CXL_PORT_SUPPORTS_68B_VH BIT(1) |
| 34 | #define CXL_PORT_SUPPORTS_256B BIT(2) |
| 35 | #define CXL_PORT_SUPPORTS_LO_256B BIT(3) |
| 36 | #define CXL_PORT_SUPPORTS_PBR BIT(4) |
| 37 | |
| 38 | #define CXL_PORT_LTSSM_DETECT 0x00 |
| 39 | #define CXL_PORT_LTSSM_POLLING 0x01 |
| 40 | #define CXL_PORT_LTSSM_CONFIGURATION 0x02 |
| 41 | #define CXL_PORT_LTSSM_RECOVERY 0x03 |
| 42 | #define CXL_PORT_LTSSM_L0 0x04 |
| 43 | #define CXL_PORT_LTSSM_L0S 0x05 |
| 44 | #define CXL_PORT_LTSSM_L1 0x06 |
| 45 | #define CXL_PORT_LTSSM_L2 0x07 |
| 46 | #define CXL_PORT_LTSSM_DISABLED 0x08 |
| 47 | #define CXL_PORT_LTSSM_LOOPBACK 0x09 |
| 48 | #define CXL_PORT_LTSSM_HOT_RESET 0x0A |
| 49 | |
| 50 | #define CXL_PORT_LINK_STATE_FLAG_LANE_REVERSED BIT(0) |
| 51 | #define CXL_PORT_LINK_STATE_FLAG_PERST_ASSERTED BIT(1) |
| 52 | #define CXL_PORT_LINK_STATE_FLAG_PRSNT BIT(2) |
| 53 | #define CXL_PORT_LINK_STATE_FLAG_POWER_OFF BIT(3) |
| 54 | |
| 55 | #define CXL_MAX_PHY_PORTS 256 |
| 56 | #define ASSERT_WAIT_TIME_MS 100 /* Assert - Deassert PERST */ |
| 57 | |
| 58 | /* Assert - Deassert PERST */ |
| 59 | typedef struct CXLPhyPortPerst { |
| 60 | bool issued_assert_perst; |
| 61 | QemuMutex lock; /* protecting assert-deassert reset request */ |
| 62 | uint64_t asrt_time; |
| 63 | QemuThread asrt_thread; /* thread for 100ms delay */ |
| 64 | } CXLPhyPortPerst; |
| 65 | |
| 66 | void cxl_init_physical_port_control(CXLPhyPortPerst *perst); |
| 67 | |
| 68 | static inline bool cxl_perst_asserted(CXLPhyPortPerst *perst) |
| 69 | { |
| 70 | return perst->issued_assert_perst || perst->asrt_time < ASSERT_WAIT_TIME_MS; |
| 71 | } |
| 72 | |
| 73 | #endif /* CXL_PORT_H */ |