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1 /*
2 * K230 GSDMA
3 *
4 * Copyright (c) 2026 Tao Ding <dingtao0430@163.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0-or-later
7 */
8
9 #ifndef HW_DMA_K230_GSDMA_H
10 #define HW_DMA_K230_GSDMA_H
11
12 #include "hw/core/sysbus.h"
13
14 #define TYPE_K230_GSDMA "riscv.k230.gsdma"
15 OBJECT_DECLARE_SIMPLE_TYPE(K230GSDMAState, K230_GSDMA)
16
17 #define K230_GSDMA_MMIO_SIZE 0x4000
18 #define K230_GSDMA_NUM_SDMA_CHANNELS 4
19
20 #define K230_GSDMA_CH_STRIDE 0x30
21 #define K230_GSDMA_CH_BASE 0x50
22
23 /* K230 SDMA request input */
24 enum {
25 K230_GSDMA_GPIO_DECOMP_CTRL_EN,
26 K230_GSDMA_GPIO_DMA_WRITE_REQ,
27 K230_GSDMA_GPIO_DMA_READ_REQ,
28 K230_GSDMA_NUM_GPIOS_IN,
29 };
30
31 /* K230 SDMA ACK output */
32 enum {
33 K230_GSDMA_GPIO_DMA_WRITE_ACK,
34 K230_GSDMA_GPIO_DMA_READ_ACK,
35 K230_GSDMA_NUM_GPIOS_OUT,
36 };
37
38 /* K230 GSDMA Registers Map */
39 #define K230_GSDMA_DMA_CH_EN 0x00
40 #define K230_GSDMA_DMA_INT_MASK 0x04
41 #define K230_GSDMA_DMA_INT_STAT 0x08
42 #define K230_GSDMA_DMA_CFG 0x0c
43 #define K230_GSDMA_GDMA_CTRL 0x10
44 #define K230_GSDMA_GDMA_LLI_BASE 0x14
45 #define K230_GSDMA_GDMA_CH_CNT0 0x18
46 #define K230_GSDMA_GDMA_CH_CNT_LAST 0x34
47 #define K230_GSDMA_GDMA_CURRENT_LLT 0x38
48 #define K230_GSDMA_DMA_WEIGHT 0x48
49
50 /* K230 GSDMA SDMA Channel Register Map */
51 #define K230_GSDMA_CH_CTL 0x00
52 #define K230_GSDMA_CH_STATUS 0x04
53 #define K230_GSDMA_CH_CFG 0x08
54 #define K230_GSDMA_CH_USR_DATA 0x0c
55 #define K230_GSDMA_CH_LLT_SADDR 0x10
56 #define K230_GSDMA_CH_CURRENT_LLT 0x14
57
58 /* K230 SDMA Control bit */
59 #define K230_GSDMA_CTL_START BIT(0)
60 #define K230_GSDMA_CTL_STOP BIT(1)
61 #define K230_GSDMA_CTL_RESUME BIT(2)
62
63 /* K230 SDMA States bit */
64 #define K230_GSDMA_SDMA_STATUS_BUSY BIT(0)
65 #define K230_GSDMA_SDMA_STATUS_PAUSE BIT(1)
66
67 /* K230 SDMA Interrupt bit */
68 #define K230_GSDMA_SDMA_DONE_INT(ch) BIT(ch)
69 #define K230_GSDMA_SDMA_ITEM_INT(ch) BIT((ch) + 4)
70 #define K230_GSDMA_SDMA_PAUSE_INT(ch) BIT((ch) + 8)
71
72
73 #define K230_GSDMA_DMA_CH_EN_MASK MAKE_64BIT_MASK(0, 5)
74 #define K230_GSDMA_DMA_CFG_RESET 0x000007ff
75
76 /* K230 SDMA Linked List bit */
77 #define K230_GSDMA_LLT_2D_MODE BIT(28)
78 #define K230_GSDMA_LLT_PAUSE BIT(29)
79 #define K230_GSDMA_LLT_NODE_INTR BIT(30)
80 #define K230_GSDMA_GDMA_LLT_GCH_SHIFT 16
81 #define K230_GSDMA_GDMA_LLT_GCH_MASK 0x7
82 #define K230_GSDMA_CH_CFG_DAT_MODE BIT(0)
83 #define K230_GSDMA_CH_CFG_USR_DATA_SIZE_SHIFT 1
84 #define K230_GSDMA_CH_CFG_USR_DATA_SIZE_MASK 0x3
85 #define K230_GSDMA_CH_CFG_DAT_ENDIAN_SHIFT 4
86 #define K230_GSDMA_CH_CFG_DAT_ENDIAN_MASK 0x3
87 #define K230_GSDMA_CH_CFG_SRC_FIXED BIT(8)
88 #define K230_GSDMA_CH_CFG_DST_FIXED BIT(9)
89 #define K230_GSDMA_CH0_CFG_DECOMP_CTRL_EN BIT(10)
90
91 /* K230 SDMA channel state */
92 typedef struct K230GSDMAChannel {
93 uint32_t ctl;
94 uint32_t status;
95 uint32_t cfg;
96 uint32_t usr_data;
97 uint32_t llt_saddr;
98 uint32_t current_llt;
99 uint32_t next_llt;
100 bool started;
101 } K230GSDMAChannel;
102
103 /* K230 SDMA Linked List */
104 typedef struct K230GSDMALLT {
105 uint32_t cfg;
106 uint32_t src_addr;
107 uint32_t line_size;
108 uint32_t line_cfg;
109 uint32_t dst_addr;
110 uint32_t next_llt_addr;
111 } K230GSDMALLT;
112
113 /* K230 GSDMA state */
114 struct K230GSDMAState {
115 SysBusDevice parent_obj;
116
117 MemoryRegion iomem;
118 qemu_irq irq;
119 qemu_irq handshake_out[K230_GSDMA_NUM_GPIOS_OUT];
120
121 uint32_t dma_ch_en;
122 uint32_t dma_int_mask;
123 uint32_t dma_int_stat;
124 uint32_t dma_cfg;
125 uint32_t dma_weight;
126
127 K230GSDMAChannel channels[K230_GSDMA_NUM_SDMA_CHANNELS];
128 };
129
130 #endif