| 1 | /* |
| 2 | * On-chip DMA controller framework. |
| 3 | * |
| 4 | * Copyright (C) 2008 Nokia Corporation |
| 5 | * Written by Andrzej Zaborowski <andrew@openedhand.com> |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 or |
| 10 | * (at your option) version 3 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef HW_SOC_DMA_H |
| 22 | #define HW_SOC_DMA_H |
| 23 | |
| 24 | #include "exec/hwaddr.h" |
| 25 | |
| 26 | struct soc_dma_s; |
| 27 | struct soc_dma_ch_s; |
| 28 | typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch); |
| 29 | |
| 30 | enum soc_dma_port_type { |
| 31 | soc_dma_port_mem, |
| 32 | soc_dma_port_other, |
| 33 | }; |
| 34 | |
| 35 | enum soc_dma_access_type { |
| 36 | soc_dma_access_const, |
| 37 | soc_dma_access_linear, |
| 38 | soc_dma_access_other, |
| 39 | }; |
| 40 | |
| 41 | struct soc_dma_ch_s { |
| 42 | /* Private */ |
| 43 | struct soc_dma_s *dma; |
| 44 | int num; |
| 45 | QEMUTimer *timer; |
| 46 | |
| 47 | /* Set by soc_dma.c */ |
| 48 | int enable; |
| 49 | int update; |
| 50 | |
| 51 | /* This should be set by dma->setup_fn(). */ |
| 52 | uint64_t bytes; |
| 53 | /* Initialised by the DMA module, call soc_dma_ch_update after writing. */ |
| 54 | enum soc_dma_access_type type[2]; |
| 55 | hwaddr vaddr[2]; /* Updated by .transfer_fn(). */ |
| 56 | |
| 57 | int running; |
| 58 | soc_dma_transfer_t transfer_fn; |
| 59 | |
| 60 | /* Set and used by the DMA module. */ |
| 61 | void *opaque; |
| 62 | }; |
| 63 | |
| 64 | struct soc_dma_s { |
| 65 | /* Following fields are set by the SoC DMA module and can be used |
| 66 | * by anybody. */ |
| 67 | uint64_t drqbmp; /* Is zeroed by soc_dma_reset() */ |
| 68 | qemu_irq *drq; |
| 69 | void *opaque; |
| 70 | int64_t freq; |
| 71 | soc_dma_transfer_t transfer_fn; |
| 72 | soc_dma_transfer_t setup_fn; |
| 73 | /* Set by soc_dma_init() for use by the DMA module. */ |
| 74 | struct soc_dma_ch_s *ch; |
| 75 | }; |
| 76 | |
| 77 | /* Call to activate or stop a DMA channel. */ |
| 78 | void soc_dma_set_request(struct soc_dma_ch_s *ch, int level); |
| 79 | /* |
| 80 | * Call after every write to one of the following fields and before |
| 81 | * calling soc_dma_set_request(ch, 1): |
| 82 | * ch->type[0...1], |
| 83 | * ch->vaddr[0...1], |
| 84 | * or after a soc_dma_port_add_mem(). |
| 85 | */ |
| 86 | void soc_dma_ch_update(struct soc_dma_ch_s *ch); |
| 87 | |
| 88 | /* The SoC should call this when the DMA module is being reset. */ |
| 89 | void soc_dma_reset(struct soc_dma_s *s); |
| 90 | struct soc_dma_s *soc_dma_init(int n); |
| 91 | |
| 92 | void soc_dma_port_add_mem(struct soc_dma_s *dma, |
| 93 | hwaddr virt_base, size_t size); |
| 94 | |
| 95 | #endif |