| 1 | /* |
| 2 | * Xilinx Platform CSU Stream DMA emulation |
| 3 | * |
| 4 | * This implementation is based on |
| 5 | * https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 or |
| 10 | * (at your option) version 3 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along |
| 18 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef XLNX_CSU_DMA_H |
| 22 | #define XLNX_CSU_DMA_H |
| 23 | |
| 24 | #include "hw/core/sysbus.h" |
| 25 | #include "hw/core/register.h" |
| 26 | #include "hw/core/ptimer.h" |
| 27 | #include "hw/core/stream.h" |
| 28 | |
| 29 | #define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" |
| 30 | |
| 31 | #define XLNX_CSU_DMA_R_MAX (0x2c / 4) |
| 32 | |
| 33 | typedef struct XlnxCSUDMA { |
| 34 | SysBusDevice busdev; |
| 35 | MemoryRegion iomem; |
| 36 | MemTxAttrs attr; |
| 37 | MemoryRegion *dma_mr; |
| 38 | AddressSpace dma_as; |
| 39 | qemu_irq irq; |
| 40 | StreamSink *tx_dev; /* Used as generic StreamSink */ |
| 41 | ptimer_state *src_timer; |
| 42 | |
| 43 | uint16_t width; |
| 44 | bool is_dst; |
| 45 | bool r_size_last_word; |
| 46 | |
| 47 | StreamCanPushNotifyFn notify; |
| 48 | void *notify_opaque; |
| 49 | |
| 50 | uint32_t regs[XLNX_CSU_DMA_R_MAX]; |
| 51 | RegisterInfo regs_info[XLNX_CSU_DMA_R_MAX]; |
| 52 | } XlnxCSUDMA; |
| 53 | |
| 54 | OBJECT_DECLARE_TYPE(XlnxCSUDMA, XlnxCSUDMAClass, XLNX_CSU_DMA) |
| 55 | |
| 56 | struct XlnxCSUDMAClass { |
| 57 | SysBusDeviceClass parent_class; |
| 58 | |
| 59 | /* |
| 60 | * read: Start a read transfer on a Xilinx CSU DMA engine |
| 61 | * |
| 62 | * @s: the Xilinx CSU DMA engine to start the transfer on |
| 63 | * @addr: the address to read |
| 64 | * @len: the number of bytes to read at 'addr' |
| 65 | * |
| 66 | * @return a MemTxResult indicating whether the operation succeeded ('len' |
| 67 | * bytes were read) or failed. |
| 68 | */ |
| 69 | MemTxResult (*read)(XlnxCSUDMA *s, hwaddr addr, uint32_t len); |
| 70 | }; |
| 71 | |
| 72 | #endif |