| 1 | /* |
| 2 | * Cadence GPIO registers definition. |
| 3 | * |
| 4 | * Author: Kuan-Jui Chiu <kchiu@axiado.com> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef CADENCE_GPIO_H |
| 10 | #define CADENCE_GPIO_H |
| 11 | |
| 12 | #include "hw/core/sysbus.h" |
| 13 | #include "qom/object.h" |
| 14 | |
| 15 | #define TYPE_CADENCE_GPIO "cadence_gpio" |
| 16 | OBJECT_DECLARE_SIMPLE_TYPE(CadenceGPIOState, CADENCE_GPIO) |
| 17 | |
| 18 | #define CDNS_GPIO_REG_SIZE 0x400 |
| 19 | #define CDNS_GPIO_NUM 32 |
| 20 | |
| 21 | #define CDNS_GPIO_BYPASS_MODE 0x00 |
| 22 | #define CDNS_GPIO_DIRECTION_MODE 0x04 |
| 23 | #define CDNS_GPIO_OUTPUT_EN 0x08 |
| 24 | #define CDNS_GPIO_OUTPUT_VALUE 0x0c |
| 25 | #define CDNS_GPIO_INPUT_VALUE 0x10 |
| 26 | #define CDNS_GPIO_IRQ_MASK 0x14 |
| 27 | #define CDNS_GPIO_IRQ_EN 0x18 |
| 28 | #define CDNS_GPIO_IRQ_DIS 0x1c |
| 29 | #define CDNS_GPIO_IRQ_STATUS 0x20 |
| 30 | #define CDNS_GPIO_IRQ_TYPE 0x24 |
| 31 | #define CDNS_GPIO_IRQ_VALUE 0x28 |
| 32 | #define CDNS_GPIO_IRQ_ANY_EDGE 0x2c |
| 33 | |
| 34 | struct CadenceGPIOState { |
| 35 | SysBusDevice parent_obj; |
| 36 | |
| 37 | MemoryRegion iomem; |
| 38 | |
| 39 | uint32_t bmr; |
| 40 | uint32_t dmr; |
| 41 | uint32_t oer; |
| 42 | uint32_t ovr; |
| 43 | uint32_t inpvr; |
| 44 | uint32_t imr; |
| 45 | uint32_t isr; |
| 46 | uint32_t itr; |
| 47 | uint32_t ivr; |
| 48 | uint32_t ioar; |
| 49 | qemu_irq irq; |
| 50 | qemu_irq output[CDNS_GPIO_NUM]; |
| 51 | }; |
| 52 | |
| 53 | #endif /* CADENCE_GPIO_H */ |