@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
h 167 lines 4.82 KB
Raw
1 /*
2 * Hexagon Baseboard System emulation.
3 *
4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
5 * SPDX-License-Identifier: GPL-2.0-or-later
6 */
7
8
9 #ifndef HW_HEXAGON_H
10 #define HW_HEXAGON_H
11
12 #include "system/memory.h"
13 #include "hw/core/boards.h"
14
15 struct hexagon_board_boot_info {
16 uint64_t ram_size;
17 const char *kernel_filename;
18 uint32_t kernel_elf_flags;
19 };
20
21 typedef enum {
22 unknown_rev = 0,
23 v66_rev = 0xa666,
24 v67_rev = 0x2667,
25 v68_rev = 0x8d68,
26 v69_rev = 0x8c69,
27 v71_rev = 0x8c71,
28 v73_rev = 0x8c73,
29 v73m_rev = 0xcc73,
30 } Rev_t;
31 #define HEXAGON_LATEST_REV v73
32 #define HEXAGON_LATEST_REV_UPPER V73
33
34 /*
35 * Config table address bases represent bits [35:16].
36 */
37 #define HEXAGON_CFG_ADDR_BASE(addr) (((addr) >> 16) & 0x0fffff)
38
39 #define HEXAGON_CFGSPACE_ENTRIES (128)
40
41 union hexagon_config_table {
42 struct {
43 /* Base address of L2TCM space */
44 uint32_t l2tcm_base;
45 uint32_t reserved0;
46 /* Base address of subsystem space */
47 uint32_t subsystem_base;
48 /* Base address of ETM space */
49 uint32_t etm_base;
50 /* Base address of L2 configuration space */
51 uint32_t l2cfg_base;
52 uint32_t reserved1;
53 /* Base address of L1S */
54 uint32_t l1s0_base;
55 /* Base address of AXI2 */
56 uint32_t axi2_lowaddr;
57 /* Base address of streamer base */
58 uint32_t streamer_base;
59 uint32_t reserved2;
60 /* Base address of fast L2VIC */
61 uint32_t fastl2vic_base;
62 /* Number of entries in JTLB */
63 uint32_t jtlb_size_entries;
64 /* Coprocessor type */
65 uint32_t coproc_present;
66 /* Number of extension execution contexts available */
67 uint32_t ext_contexts;
68 /* Base address of Hexagon Vector Tightly Coupled Memory (VTCM) */
69 uint32_t vtcm_base;
70 /* Size of VTCM (in KB) */
71 uint32_t vtcm_size_kb;
72 /* L2 tag size */
73 uint32_t l2tag_size;
74 /* Amount of physical L2 memory in released version */
75 uint32_t l2ecomem_size;
76 /* Hardware threads available on the core */
77 uint32_t thread_enable_mask;
78 /* Base address of the ECC registers */
79 uint32_t eccreg_base;
80 /* L2 line size */
81 uint32_t l2line_size;
82 /* Small Core processor (also implies audio extension) */
83 uint32_t tiny_core;
84 /* Size of L2TCM */
85 uint32_t l2itcm_size;
86 /* Base address of L2-ITCM */
87 uint32_t l2itcm_base;
88 uint32_t reserved3;
89 /* DTM is present */
90 uint32_t dtm_present;
91 /* Version of the DMA */
92 uint32_t dma_version;
93 /* Native HVX vector length in log of bytes */
94 uint32_t hvx_vec_log_length;
95 /* Core ID of the multi-core */
96 uint32_t core_id;
97 /* Number of multi-core cores */
98 uint32_t core_count;
99 uint32_t coproc2_reg0;
100 uint32_t coproc2_reg1;
101 /* Supported HVX vector length */
102 uint32_t v2x_mode;
103 uint32_t coproc2_reg2;
104 uint32_t coproc2_reg3;
105 uint32_t coproc2_reg4;
106 uint32_t coproc2_reg5;
107 uint32_t coproc2_reg6;
108 uint32_t coproc2_reg7;
109 /* Voltage droop mitigation technique parameter */
110 uint32_t acd_preset;
111 /* Voltage droop mitigation technique parameter */
112 uint32_t mnd_preset;
113 /* L1 data cache size (in KB) */
114 uint32_t l1d_size_kb;
115 /* L1 instruction cache size in (KB) */
116 uint32_t l1i_size_kb;
117 /* L1 data cache write policy: see HexagonL1WritePolicy */
118 uint32_t l1d_write_policy;
119 /* VTCM bank width */
120 uint32_t vtcm_bank_width;
121 uint32_t reserved4;
122 uint32_t reserved5;
123 uint32_t reserved6;
124 uint32_t coproc2_cvt_mpy_size;
125 uint32_t consistency_domain;
126 uint32_t capacity_domain;
127 uint32_t axi3_lowaddr;
128 uint32_t coproc2_int8_subcolumns;
129 uint32_t corecfg_present;
130 uint32_t coproc2_fp16_acc_exp;
131 uint32_t AXIM2_secondary_base;
132 };
133 uint32_t raw[HEXAGON_CFGSPACE_ENTRIES];
134 };
135
136 struct hexagon_machine_config {
137 /* Base address of config table */
138 uint32_t cfgbase;
139 /* Size of L2 TCM */
140 uint32_t l2tcm_size;
141 /* Base address of L2VIC */
142 uint32_t l2vic_base;
143 /* Size of L2VIC region */
144 uint32_t l2vic_size;
145 /* QTimer csr base */
146 uint32_t csr_base;
147 uint32_t qtmr_region;
148 union hexagon_config_table cfgtable;
149 };
150
151 #define TYPE_HEXAGON_COMMON_MACHINE "hexagon-common-machine"
152 OBJECT_DECLARE_SIMPLE_TYPE(HexagonCommonMachineState, HEXAGON_COMMON_MACHINE)
153
154 struct HexagonCommonMachineState {
155 MachineState parent_obj;
156
157 MemoryRegion ram;
158 MemoryRegion cfgtable_rom;
159 MemoryRegion vtcm;
160 DeviceState *cluster;
161 DeviceState *l2vic;
162 DeviceState *qtimer;
163 DeviceState *glob_regs;
164 DeviceState *tlb;
165 };
166
167 #endif