| 1 | /* |
| 2 | * Hexagon Global Registers QOM Object |
| 3 | * |
| 4 | * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. |
| 5 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 6 | */ |
| 7 | |
| 8 | #ifndef HEXAGON_GLOBALREG_H |
| 9 | #define HEXAGON_GLOBALREG_H |
| 10 | |
| 11 | #include "hw/core/qdev.h" |
| 12 | #include "hw/core/sysbus.h" |
| 13 | #include "hw/intc/hex-l2vic.h" |
| 14 | #include "hw/timer/qct-qtimer.h" |
| 15 | #include "qom/object.h" |
| 16 | #include "target/hexagon/cpu.h" |
| 17 | |
| 18 | #define TYPE_HEXAGON_GLOBALREG "hexagon-globalreg" |
| 19 | OBJECT_DECLARE_SIMPLE_TYPE(HexagonGlobalRegState, HEXAGON_GLOBALREG) |
| 20 | |
| 21 | struct HexagonGlobalRegState { |
| 22 | SysBusDevice parent_obj; |
| 23 | |
| 24 | /* Array of system registers */ |
| 25 | uint32_t regs[NUM_SREGS]; |
| 26 | |
| 27 | /* L2VIC interface used to back the VID/VID1 registers */ |
| 28 | HexL2VicInterface *l2vic; |
| 29 | |
| 30 | /* QTimer interface used to back the TIMERLO/TIMERHI registers */ |
| 31 | QctQtimerInterface *qtimer; |
| 32 | |
| 33 | /* Global performance cycle counter base */ |
| 34 | uint64_t g_pcycle_base; |
| 35 | |
| 36 | /* Properties for global register reset values */ |
| 37 | uint32_t boot_evb; /* Boot Exception Vector Base (HEX_SREG_EVB) */ |
| 38 | uint64_t config_table_addr; /* Configuration table base */ |
| 39 | uint32_t dsp_rev; /* DSP revision register (HEX_SREG_REV) */ |
| 40 | |
| 41 | /* ISDB properties */ |
| 42 | bool isdben_etm_enable; /* ISDB ETM enable bit */ |
| 43 | bool isdben_dfd_enable; /* ISDB DFD enable bit */ |
| 44 | bool isdben_trusted; /* ISDB trusted mode bit */ |
| 45 | bool isdben_secure; /* ISDB secure mode bit */ |
| 46 | }; |
| 47 | |
| 48 | /* Public interface functions */ |
| 49 | uint32_t hexagon_globalreg_read(HexagonGlobalRegState *s, uint32_t reg, |
| 50 | uint32_t htid); |
| 51 | void hexagon_globalreg_write(HexagonGlobalRegState *s, uint32_t reg, |
| 52 | uint32_t value, uint32_t htid); |
| 53 | uint32_t hexagon_globalreg_masked_value(HexagonGlobalRegState *s, uint32_t reg, |
| 54 | uint32_t value); |
| 55 | void hexagon_globalreg_write_masked(HexagonGlobalRegState *s, uint32_t reg, |
| 56 | uint32_t value); |
| 57 | |
| 58 | /* Global performance cycle counter access */ |
| 59 | uint64_t hexagon_globalreg_get_pcycle_base(HexagonGlobalRegState *s); |
| 60 | void hexagon_globalreg_set_pcycle_base(HexagonGlobalRegState *s, |
| 61 | uint64_t value); |
| 62 | |
| 63 | #endif /* HEXAGON_GLOBALREG_H */ |