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1 /*
2 * Userspace interfaces for /dev/mshv* devices and derived fds
3 *
4 * SPDX-License-Identifier: GPL-2.0-or-later
5 */
6
7 #ifndef HW_HYPERV_HVGDK_MINI_H
8 #define HW_HYPERV_HVGDK_MINI_H
9
10 #define MSHV_IOCTL 0xB8
11
12 /* Hyper-V specific model specific registers (MSRs) */
13
14 /* HV_X64_SYNTHETIC_MSR */
15 #define HV_X64_MSR_GUEST_OS_ID 0x40000000
16 #define HV_X64_MSR_HYPERCALL 0x40000001
17 #define HV_X64_MSR_VP_INDEX 0x40000002
18 #define HV_X64_MSR_RESET 0x40000003
19 #define HV_X64_MSR_VP_RUNTIME 0x40000010
20 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020
21 #define HV_X64_MSR_REFERENCE_TSC 0x40000021
22 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022
23 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023
24
25 typedef enum hv_register_name {
26 /* VP Management Registers */
27 HV_REGISTER_INTERNAL_ACTIVITY_STATE = 0x00000004,
28
29 /* Pending Interruption Register */
30 HV_REGISTER_PENDING_INTERRUPTION = 0x00010002,
31 HV_REGISTER_INTERRUPT_STATE = 0x00010003,
32 HV_REGISTER_PENDING_EVENT0 = 0x00010004,
33 HV_REGISTER_PENDING_EVENT1 = 0x00010005,
34
35 /* X64 User-Mode Registers */
36 HV_X64_REGISTER_RAX = 0x00020000,
37 HV_X64_REGISTER_RCX = 0x00020001,
38 HV_X64_REGISTER_RDX = 0x00020002,
39 HV_X64_REGISTER_RBX = 0x00020003,
40 HV_X64_REGISTER_RSP = 0x00020004,
41 HV_X64_REGISTER_RBP = 0x00020005,
42 HV_X64_REGISTER_RSI = 0x00020006,
43 HV_X64_REGISTER_RDI = 0x00020007,
44 HV_X64_REGISTER_R8 = 0x00020008,
45 HV_X64_REGISTER_R9 = 0x00020009,
46 HV_X64_REGISTER_R10 = 0x0002000A,
47 HV_X64_REGISTER_R11 = 0x0002000B,
48 HV_X64_REGISTER_R12 = 0x0002000C,
49 HV_X64_REGISTER_R13 = 0x0002000D,
50 HV_X64_REGISTER_R14 = 0x0002000E,
51 HV_X64_REGISTER_R15 = 0x0002000F,
52 HV_X64_REGISTER_RIP = 0x00020010,
53 HV_X64_REGISTER_RFLAGS = 0x00020011,
54
55 /* X64 Floating Point and Vector Registers */
56 HV_X64_REGISTER_XMM0 = 0x00030000,
57 HV_X64_REGISTER_XMM1 = 0x00030001,
58 HV_X64_REGISTER_XMM2 = 0x00030002,
59 HV_X64_REGISTER_XMM3 = 0x00030003,
60 HV_X64_REGISTER_XMM4 = 0x00030004,
61 HV_X64_REGISTER_XMM5 = 0x00030005,
62 HV_X64_REGISTER_XMM6 = 0x00030006,
63 HV_X64_REGISTER_XMM7 = 0x00030007,
64 HV_X64_REGISTER_XMM8 = 0x00030008,
65 HV_X64_REGISTER_XMM9 = 0x00030009,
66 HV_X64_REGISTER_XMM10 = 0x0003000A,
67 HV_X64_REGISTER_XMM11 = 0x0003000B,
68 HV_X64_REGISTER_XMM12 = 0x0003000C,
69 HV_X64_REGISTER_XMM13 = 0x0003000D,
70 HV_X64_REGISTER_XMM14 = 0x0003000E,
71 HV_X64_REGISTER_XMM15 = 0x0003000F,
72 HV_X64_REGISTER_FP_MMX0 = 0x00030010,
73 HV_X64_REGISTER_FP_MMX1 = 0x00030011,
74 HV_X64_REGISTER_FP_MMX2 = 0x00030012,
75 HV_X64_REGISTER_FP_MMX3 = 0x00030013,
76 HV_X64_REGISTER_FP_MMX4 = 0x00030014,
77 HV_X64_REGISTER_FP_MMX5 = 0x00030015,
78 HV_X64_REGISTER_FP_MMX6 = 0x00030016,
79 HV_X64_REGISTER_FP_MMX7 = 0x00030017,
80 HV_X64_REGISTER_FP_CONTROL_STATUS = 0x00030018,
81 HV_X64_REGISTER_XMM_CONTROL_STATUS = 0x00030019,
82
83 /* X64 Control Registers */
84 HV_X64_REGISTER_CR0 = 0x00040000,
85 HV_X64_REGISTER_CR2 = 0x00040001,
86 HV_X64_REGISTER_CR3 = 0x00040002,
87 HV_X64_REGISTER_CR4 = 0x00040003,
88 HV_X64_REGISTER_CR8 = 0x00040004,
89 HV_X64_REGISTER_XFEM = 0x00040005,
90
91 /* X64 Segment Registers */
92 HV_X64_REGISTER_ES = 0x00060000,
93 HV_X64_REGISTER_CS = 0x00060001,
94 HV_X64_REGISTER_SS = 0x00060002,
95 HV_X64_REGISTER_DS = 0x00060003,
96 HV_X64_REGISTER_FS = 0x00060004,
97 HV_X64_REGISTER_GS = 0x00060005,
98 HV_X64_REGISTER_LDTR = 0x00060006,
99 HV_X64_REGISTER_TR = 0x00060007,
100
101 /* X64 Table Registers */
102 HV_X64_REGISTER_IDTR = 0x00070000,
103 HV_X64_REGISTER_GDTR = 0x00070001,
104
105 /* X64 Virtualized MSRs */
106 HV_X64_REGISTER_TSC = 0x00080000,
107 HV_X64_REGISTER_EFER = 0x00080001,
108 HV_X64_REGISTER_KERNEL_GS_BASE = 0x00080002,
109 HV_X64_REGISTER_APIC_BASE = 0x00080003,
110 HV_X64_REGISTER_PAT = 0x00080004,
111 HV_X64_REGISTER_SYSENTER_CS = 0x00080005,
112 HV_X64_REGISTER_SYSENTER_EIP = 0x00080006,
113 HV_X64_REGISTER_SYSENTER_ESP = 0x00080007,
114 HV_X64_REGISTER_STAR = 0x00080008,
115 HV_X64_REGISTER_LSTAR = 0x00080009,
116 HV_X64_REGISTER_CSTAR = 0x0008000A,
117 HV_X64_REGISTER_SFMASK = 0x0008000B,
118 HV_X64_REGISTER_INITIAL_APIC_ID = 0x0008000C,
119
120 /* X64 Cache control MSRs */
121 HV_X64_REGISTER_MSR_MTRR_CAP = 0x0008000D,
122 HV_X64_REGISTER_MSR_MTRR_DEF_TYPE = 0x0008000E,
123 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE0 = 0x00080010,
124 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE1 = 0x00080011,
125 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE2 = 0x00080012,
126 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE3 = 0x00080013,
127 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE4 = 0x00080014,
128 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE5 = 0x00080015,
129 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE6 = 0x00080016,
130 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE7 = 0x00080017,
131 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE8 = 0x00080018,
132 HV_X64_REGISTER_MSR_MTRR_PHYS_BASE9 = 0x00080019,
133 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEA = 0x0008001A,
134 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEB = 0x0008001B,
135 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEC = 0x0008001C,
136 HV_X64_REGISTER_MSR_MTRR_PHYS_BASED = 0x0008001D,
137 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEE = 0x0008001E,
138 HV_X64_REGISTER_MSR_MTRR_PHYS_BASEF = 0x0008001F,
139 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK0 = 0x00080040,
140 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK1 = 0x00080041,
141 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK2 = 0x00080042,
142 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK3 = 0x00080043,
143 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK4 = 0x00080044,
144 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK5 = 0x00080045,
145 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK6 = 0x00080046,
146 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK7 = 0x00080047,
147 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK8 = 0x00080048,
148 HV_X64_REGISTER_MSR_MTRR_PHYS_MASK9 = 0x00080049,
149 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKA = 0x0008004A,
150 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKB = 0x0008004B,
151 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKC = 0x0008004C,
152 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKD = 0x0008004D,
153 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKE = 0x0008004E,
154 HV_X64_REGISTER_MSR_MTRR_PHYS_MASKF = 0x0008004F,
155 HV_X64_REGISTER_MSR_MTRR_FIX64K00000 = 0x00080070,
156 HV_X64_REGISTER_MSR_MTRR_FIX16K80000 = 0x00080071,
157 HV_X64_REGISTER_MSR_MTRR_FIX16KA0000 = 0x00080072,
158 HV_X64_REGISTER_MSR_MTRR_FIX4KC0000 = 0x00080073,
159 HV_X64_REGISTER_MSR_MTRR_FIX4KC8000 = 0x00080074,
160 HV_X64_REGISTER_MSR_MTRR_FIX4KD0000 = 0x00080075,
161 HV_X64_REGISTER_MSR_MTRR_FIX4KD8000 = 0x00080076,
162 HV_X64_REGISTER_MSR_MTRR_FIX4KE0000 = 0x00080077,
163 HV_X64_REGISTER_MSR_MTRR_FIX4KE8000 = 0x00080078,
164 HV_X64_REGISTER_MSR_MTRR_FIX4KF0000 = 0x00080079,
165 HV_X64_REGISTER_MSR_MTRR_FIX4KF8000 = 0x0008007A,
166
167 HV_X64_REGISTER_TSC_AUX = 0x0008007B,
168 HV_X64_REGISTER_BNDCFGS = 0x0008007C,
169 HV_X64_REGISTER_DEBUG_CTL = 0x0008007D,
170
171 /* Available */
172
173 HV_X64_REGISTER_SPEC_CTRL = 0x00080084,
174 HV_X64_REGISTER_TSC_DEADLINE = 0x00080095,
175 HV_X64_REGISTER_TSC_ADJUST = 0x00080096,
176
177 /* CET / Shadow Stack */
178 HV_X64_REGISTER_U_XSS = 0x0008008B,
179 HV_X64_REGISTER_U_CET = 0x0008008C,
180 HV_X64_REGISTER_S_CET = 0x0008008D,
181 HV_X64_REGISTER_SSP = 0x0008008E,
182 HV_X64_REGISTER_PL0_SSP = 0x0008008F,
183 HV_X64_REGISTER_PL1_SSP = 0x00080090,
184 HV_X64_REGISTER_PL2_SSP = 0x00080091,
185 HV_X64_REGISTER_PL3_SSP = 0x00080092,
186 HV_X64_REGISTER_INTERRUPT_SSP_TABLE_ADDR = 0x00080093,
187
188 /* Other MSRs */
189 HV_X64_REGISTER_MSR_IA32_MISC_ENABLE = 0x000800A0,
190
191 /* Misc */
192 HV_X64_REGISTER_HYPERCALL = 0x00090001,
193 HV_REGISTER_GUEST_OS_ID = 0x00090002,
194 HV_REGISTER_REFERENCE_TSC = 0x00090017,
195
196 /* Hypervisor-defined Registers (Synic) */
197 HV_REGISTER_SINT0 = 0x000A0000,
198 HV_REGISTER_SINT1 = 0x000A0001,
199 HV_REGISTER_SINT2 = 0x000A0002,
200 HV_REGISTER_SINT3 = 0x000A0003,
201 HV_REGISTER_SINT4 = 0x000A0004,
202 HV_REGISTER_SINT5 = 0x000A0005,
203 HV_REGISTER_SINT6 = 0x000A0006,
204 HV_REGISTER_SINT7 = 0x000A0007,
205 HV_REGISTER_SINT8 = 0x000A0008,
206 HV_REGISTER_SINT9 = 0x000A0009,
207 HV_REGISTER_SINT10 = 0x000A000A,
208 HV_REGISTER_SINT11 = 0x000A000B,
209 HV_REGISTER_SINT12 = 0x000A000C,
210 HV_REGISTER_SINT13 = 0x000A000D,
211 HV_REGISTER_SINT14 = 0x000A000E,
212 HV_REGISTER_SINT15 = 0x000A000F,
213 HV_REGISTER_SCONTROL = 0x000A0010,
214 HV_REGISTER_SVERSION = 0x000A0011,
215 HV_REGISTER_SIEFP = 0x000A0012,
216 HV_REGISTER_SIMP = 0x000A0013,
217 HV_REGISTER_EOM = 0x000A0014,
218 HV_REGISTER_SIRBP = 0x000A0015,
219 } hv_register_name;
220
221 enum hv_intercept_type {
222 HV_INTERCEPT_TYPE_X64_IO_PORT = 0X00000000,
223 HV_INTERCEPT_TYPE_X64_MSR = 0X00000001,
224 HV_INTERCEPT_TYPE_X64_CPUID = 0X00000002,
225 HV_INTERCEPT_TYPE_EXCEPTION = 0X00000003,
226
227 /* Used to be HV_INTERCEPT_TYPE_REGISTER */
228 HV_INTERCEPT_TYPE_RESERVED0 = 0X00000004,
229 HV_INTERCEPT_TYPE_MMIO = 0X00000005,
230 HV_INTERCEPT_TYPE_X64_GLOBAL_CPUID = 0X00000006,
231 HV_INTERCEPT_TYPE_X64_APIC_SMI = 0X00000007,
232 HV_INTERCEPT_TYPE_HYPERCALL = 0X00000008,
233
234 HV_INTERCEPT_TYPE_X64_APIC_INIT_SIPI = 0X00000009,
235 HV_INTERCEPT_MC_UPDATE_PATCH_LEVEL_MSR_READ = 0X0000000A,
236
237 HV_INTERCEPT_TYPE_X64_APIC_WRITE = 0X0000000B,
238 HV_INTERCEPT_TYPE_X64_MSR_INDEX = 0X0000000C,
239 HV_INTERCEPT_TYPE_MAX,
240 HV_INTERCEPT_TYPE_INVALID = 0XFFFFFFFF,
241 };
242
243 struct hv_u128 {
244 uint64_t low_part;
245 uint64_t high_part;
246 } QEMU_PACKED;
247
248 union hv_x64_xmm_control_status_register {
249 struct hv_u128 as_uint128;
250 struct {
251 union {
252 /* long mode */
253 uint64_t last_fp_rdp;
254 /* 32 bit mode */
255 struct {
256 uint32_t last_fp_dp;
257 uint16_t last_fp_ds;
258 uint16_t padding;
259 };
260 };
261 uint32_t xmm_status_control;
262 uint32_t xmm_status_control_mask;
263 };
264 };
265
266 union hv_x64_fp_register {
267 struct hv_u128 as_uint128;
268 struct {
269 uint64_t mantissa;
270 uint64_t biased_exponent:15;
271 uint64_t sign:1;
272 uint64_t reserved:48;
273 };
274 };
275
276 union hv_x64_pending_exception_event {
277 uint64_t as_uint64[2];
278 struct {
279 uint32_t event_pending:1;
280 uint32_t event_type:3;
281 uint32_t reserved0:4;
282 uint32_t deliver_error_code:1;
283 uint32_t reserved1:7;
284 uint32_t vector:16;
285 uint32_t error_code;
286 uint64_t exception_parameter;
287 };
288 };
289
290 union hv_x64_pending_virtualization_fault_event {
291 uint64_t as_uint64[2];
292 struct {
293 uint32_t event_pending:1;
294 uint32_t event_type:3;
295 uint32_t reserved0:4;
296 uint32_t reserved1:8;
297 uint32_t parameter0:16;
298 uint32_t code;
299 uint64_t parameter1;
300 };
301 };
302
303 union hv_x64_pending_interruption_register {
304 uint64_t as_uint64;
305 struct {
306 uint32_t interruption_pending:1;
307 uint32_t interruption_type:3;
308 uint32_t deliver_error_code:1;
309 uint32_t instruction_length:4;
310 uint32_t nested_event:1;
311 uint32_t reserved:6;
312 uint32_t interruption_vector:16;
313 uint32_t error_code;
314 };
315 };
316
317 union hv_x64_register_sev_control {
318 uint64_t as_uint64;
319 struct {
320 uint64_t enable_encrypted_state:1;
321 uint64_t reserved_z:11;
322 uint64_t vmsa_gpa_page_number:52;
323 };
324 };
325
326 union hv_x64_msr_npiep_config_contents {
327 uint64_t as_uint64;
328 struct {
329 /*
330 * These bits enable instruction execution prevention for
331 * specific instructions.
332 */
333 uint64_t prevents_gdt:1;
334 uint64_t prevents_idt:1;
335 uint64_t prevents_ldt:1;
336 uint64_t prevents_tr:1;
337
338 /* The reserved bits must always be 0. */
339 uint64_t reserved:60;
340 };
341 };
342
343 typedef struct hv_x64_segment_register {
344 uint64_t base;
345 uint32_t limit;
346 uint16_t selector;
347 union {
348 struct {
349 uint16_t segment_type:4;
350 uint16_t non_system_segment:1;
351 uint16_t descriptor_privilege_level:2;
352 uint16_t present:1;
353 uint16_t reserved:4;
354 uint16_t available:1;
355 uint16_t _long:1;
356 uint16_t _default:1;
357 uint16_t granularity:1;
358 };
359 uint16_t attributes;
360 };
361 } QEMU_PACKED hv_x64_segment_register;
362
363 typedef struct hv_x64_table_register {
364 uint16_t pad[3];
365 uint16_t limit;
366 uint64_t base;
367 } QEMU_PACKED hv_x64_table_register;
368
369 union hv_x64_fp_control_status_register {
370 struct hv_u128 as_uint128;
371 struct {
372 uint16_t fp_control;
373 uint16_t fp_status;
374 uint8_t fp_tag;
375 uint8_t reserved;
376 uint16_t last_fp_op;
377 union {
378 /* long mode */
379 uint64_t last_fp_rip;
380 /* 32 bit mode */
381 struct {
382 uint32_t last_fp_eip;
383 uint16_t last_fp_cs;
384 uint16_t padding;
385 };
386 };
387 };
388 };
389
390 /* General Hypervisor Register Content Definitions */
391
392 union hv_explicit_suspend_register {
393 uint64_t as_uint64;
394 struct {
395 uint64_t suspended:1;
396 uint64_t reserved:63;
397 };
398 };
399
400 union hv_internal_activity_register {
401 uint64_t as_uint64;
402
403 struct {
404 uint64_t startup_suspend:1;
405 uint64_t halt_suspend:1;
406 uint64_t idle_suspend:1;
407 uint64_t rsvd_z:61;
408 };
409 };
410
411 union hv_x64_interrupt_state_register {
412 uint64_t as_uint64;
413 struct {
414 uint64_t interrupt_shadow:1;
415 uint64_t nmi_masked:1;
416 uint64_t reserved:62;
417 };
418 };
419
420 union hv_intercept_suspend_register {
421 uint64_t as_uint64;
422 struct {
423 uint64_t suspended:1;
424 uint64_t reserved:63;
425 };
426 };
427
428 typedef union hv_register_value {
429 struct hv_u128 reg128;
430 uint64_t reg64;
431 uint32_t reg32;
432 uint16_t reg16;
433 uint8_t reg8;
434 union hv_x64_fp_register fp;
435 union hv_x64_fp_control_status_register fp_control_status;
436 union hv_x64_xmm_control_status_register xmm_control_status;
437 struct hv_x64_segment_register segment;
438 struct hv_x64_table_register table;
439 union hv_explicit_suspend_register explicit_suspend;
440 union hv_intercept_suspend_register intercept_suspend;
441 union hv_internal_activity_register internal_activity;
442 union hv_x64_interrupt_state_register interrupt_state;
443 union hv_x64_pending_interruption_register pending_interruption;
444 union hv_x64_msr_npiep_config_contents npiep_config;
445 union hv_x64_pending_exception_event pending_exception_event;
446 union hv_x64_pending_virtualization_fault_event
447 pending_virtualization_fault_event;
448 union hv_x64_register_sev_control sev_control;
449 } hv_register_value;
450
451 /*
452 * This struct is __packed in the kernel. Since all members are naturally
453 * aligned, we can omit QEMU_PACKED to avoid address-of-packed-member warnings.
454 */
455 typedef struct hv_register_assoc {
456 uint32_t name; /* enum hv_register_name */
457 uint32_t reserved1;
458 uint64_t reserved2;
459 union hv_register_value value;
460 } hv_register_assoc;
461
462 union hv_input_vtl {
463 uint8_t as_uint8;
464 struct {
465 uint8_t target_vtl:4;
466 uint8_t use_target_vtl:1;
467 uint8_t reserved_z:3;
468 };
469 };
470
471 typedef struct hv_input_get_vp_registers {
472 uint64_t partition_id;
473 uint32_t vp_index;
474 union hv_input_vtl input_vtl;
475 uint8_t rsvd_z8;
476 uint16_t rsvd_z16;
477 uint32_t names[];
478 } QEMU_PACKED hv_input_get_vp_registers;
479
480 typedef struct hv_input_set_vp_registers {
481 uint64_t partition_id;
482 uint32_t vp_index;
483 union hv_input_vtl input_vtl;
484 uint8_t rsvd_z8;
485 uint16_t rsvd_z16;
486 struct hv_register_assoc elements[];
487 } QEMU_PACKED hv_input_set_vp_registers;
488
489 #define MSHV_VP_MAX_REGISTERS 128
490
491 union hv_interrupt_control {
492 uint64_t as_uint64;
493 struct {
494 uint32_t interrupt_type; /* enum hv_interrupt type */
495 uint32_t level_triggered:1;
496 uint32_t logical_dest_mode:1;
497 uint32_t rsvd:30;
498 };
499 };
500
501 struct hv_input_assert_virtual_interrupt {
502 uint64_t partition_id;
503 union hv_interrupt_control control;
504 uint64_t dest_addr; /* cpu's apic id */
505 uint32_t vector;
506 uint8_t target_vtl;
507 uint8_t rsvd_z0;
508 uint16_t rsvd_z1;
509 } QEMU_PACKED;
510
511 /* Flags for dirty mask of hv_vp_register_page */
512 enum hv_x64_register_class_type {
513 HV_X64_REGISTER_CLASS_GENERAL = 0,
514 HV_X64_REGISTER_CLASS_IP = 1,
515 HV_X64_REGISTER_CLASS_XMM = 2,
516 HV_X64_REGISTER_CLASS_SEGMENT = 3,
517 HV_X64_REGISTER_CLASS_FLAGS = 4,
518 };
519
520 #define HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT 7
521
522 union hv_vp_register_page_interrupt_vectors {
523 uint64_t as_uint64;
524 struct {
525 uint8_t vector_count;
526 uint8_t vector[HV_VP_REGISTER_PAGE_MAX_VECTOR_COUNT];
527 };
528 };
529
530 struct hv_vp_register_page {
531 uint16_t version;
532 uint8_t isvalid;
533 uint8_t rsvdz;
534 uint32_t dirty;
535
536 union {
537 struct {
538 /* General purpose registers (HV_X64_REGISTER_CLASS_GENERAL) */
539 union {
540 struct {
541 uint64_t rax;
542 uint64_t rcx;
543 uint64_t rdx;
544 uint64_t rbx;
545 uint64_t rsp;
546 uint64_t rbp;
547 uint64_t rsi;
548 uint64_t rdi;
549 uint64_t r8;
550 uint64_t r9;
551 uint64_t r10;
552 uint64_t r11;
553 uint64_t r12;
554 uint64_t r13;
555 uint64_t r14;
556 uint64_t r15;
557 } QEMU_PACKED;
558
559 uint64_t gp_registers[16];
560 };
561 /* Instruction pointer (HV_X64_REGISTER_CLASS_IP) */
562 uint64_t rip;
563 /* Flags (HV_X64_REGISTER_CLASS_FLAGS) */
564 uint64_t rflags;
565 } QEMU_PACKED;
566
567 uint64_t registers[18];
568 };
569 uint8_t reserved[8];
570 /* Volatile XMM registers (HV_X64_REGISTER_CLASS_XMM) */
571 union {
572 struct {
573 struct hv_u128 xmm0;
574 struct hv_u128 xmm1;
575 struct hv_u128 xmm2;
576 struct hv_u128 xmm3;
577 struct hv_u128 xmm4;
578 struct hv_u128 xmm5;
579 } QEMU_PACKED;
580
581 struct hv_u128 xmm_registers[6];
582 };
583 /* Segment registers (HV_X64_REGISTER_CLASS_SEGMENT) */
584 union {
585 struct {
586 struct hv_x64_segment_register es;
587 struct hv_x64_segment_register cs;
588 struct hv_x64_segment_register ss;
589 struct hv_x64_segment_register ds;
590 struct hv_x64_segment_register fs;
591 struct hv_x64_segment_register gs;
592 } QEMU_PACKED;
593
594 struct hv_x64_segment_register segment_registers[6];
595 };
596 /* Misc. control registers (cannot be set via this interface) */
597 uint64_t cr0;
598 uint64_t cr3;
599 uint64_t cr4;
600 uint64_t cr8;
601 uint64_t efer;
602 uint64_t dr7;
603 union hv_x64_pending_interruption_register pending_interruption;
604 union hv_x64_interrupt_state_register interrupt_state;
605 uint64_t instruction_emulation_hints;
606 uint64_t xfem;
607
608 uint8_t reserved1[0x100];
609
610 /* Interrupts injected as part of HvCallDispatchVp. */
611 union hv_vp_register_page_interrupt_vectors interrupt_vectors;
612 } QEMU_PACKED;
613
614 /* /dev/mshv */
615 #define MSHV_CREATE_PARTITION _IOW(MSHV_IOCTL, 0x00, struct mshv_create_partition)
616 #define MSHV_CREATE_VP _IOW(MSHV_IOCTL, 0x01, struct mshv_create_vp)
617
618 /* Partition fds created with MSHV_CREATE_PARTITION */
619 #define MSHV_INITIALIZE_PARTITION _IO(MSHV_IOCTL, 0x00)
620 #define MSHV_SET_GUEST_MEMORY _IOW(MSHV_IOCTL, 0x02, struct mshv_user_mem_region)
621 #define MSHV_IRQFD _IOW(MSHV_IOCTL, 0x03, struct mshv_user_irqfd)
622 #define MSHV_IOEVENTFD _IOW(MSHV_IOCTL, 0x04, struct mshv_user_ioeventfd)
623 #define MSHV_SET_MSI_ROUTING _IOW(MSHV_IOCTL, 0x05, struct mshv_user_irq_table)
624
625 /*
626 ********************************
627 * VP APIs for child partitions *
628 ********************************
629 */
630
631 /*
632 * This struct is __packed in the kernel, but since all members are naturally
633 * aligned, so we can omit QEMU_PACKED to avoid address-of-packed-member
634 * warnings.
635 */
636 struct hv_local_interrupt_controller_state {
637 /* HV_X64_INTERRUPT_CONTROLLER_STATE */
638 uint32_t apic_id;
639 uint32_t apic_version;
640 uint32_t apic_ldr;
641 uint32_t apic_dfr;
642 uint32_t apic_spurious;
643 uint32_t apic_isr[8];
644 uint32_t apic_tmr[8];
645 uint32_t apic_irr[8];
646 uint32_t apic_esr;
647 uint32_t apic_icr_high;
648 uint32_t apic_icr_low;
649 uint32_t apic_lvt_timer;
650 uint32_t apic_lvt_thermal;
651 uint32_t apic_lvt_perfmon;
652 uint32_t apic_lvt_lint0;
653 uint32_t apic_lvt_lint1;
654 uint32_t apic_lvt_error;
655 uint32_t apic_lvt_cmci;
656 uint32_t apic_error_status;
657 uint32_t apic_initial_count;
658 uint32_t apic_counter_value;
659 uint32_t apic_divide_configuration;
660 uint32_t apic_remote_read;
661 };
662
663 /* Generic hypercall */
664 #define MSHV_ROOT_HVCALL _IOWR(MSHV_IOCTL, 0x07, struct mshv_root_hvcall)
665
666 /* From hvgdk_mini.h */
667
668 #define HV_X64_MSR_GUEST_OS_ID 0x40000000
669 #define HV_X64_MSR_SINT0 0x40000090
670 #define HV_X64_MSR_SINT1 0x40000091
671 #define HV_X64_MSR_SINT2 0x40000092
672 #define HV_X64_MSR_SINT3 0x40000093
673 #define HV_X64_MSR_SINT4 0x40000094
674 #define HV_X64_MSR_SINT5 0x40000095
675 #define HV_X64_MSR_SINT6 0x40000096
676 #define HV_X64_MSR_SINT7 0x40000097
677 #define HV_X64_MSR_SINT8 0x40000098
678 #define HV_X64_MSR_SINT9 0x40000099
679 #define HV_X64_MSR_SINT10 0x4000009A
680 #define HV_X64_MSR_SINT11 0x4000009B
681 #define HV_X64_MSR_SINT12 0x4000009C
682 #define HV_X64_MSR_SINT13 0x4000009D
683 #define HV_X64_MSR_SINT14 0x4000009E
684 #define HV_X64_MSR_SINT15 0x4000009F
685 #define HV_X64_MSR_SCONTROL 0x40000080
686 #define HV_X64_MSR_SIEFP 0x40000082
687 #define HV_X64_MSR_SIMP 0x40000083
688 #define HV_X64_MSR_REFERENCE_TSC 0x40000021
689 #define HV_X64_MSR_EOM 0x40000084
690
691 /* Define port identifier type. */
692 union hv_port_id {
693 uint32_t asuint32_t;
694 struct {
695 uint32_t id:24;
696 uint32_t reserved:8;
697 };
698 };
699
700 #define HV_MESSAGE_SIZE (256)
701 #define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
702 #define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
703
704 /* Define hypervisor message types. */
705 enum hv_message_type {
706 HVMSG_NONE = 0x00000000,
707
708 /* Memory access messages. */
709 HVMSG_UNMAPPED_GPA = 0x80000000,
710 HVMSG_GPA_INTERCEPT = 0x80000001,
711 HVMSG_UNACCEPTED_GPA = 0x80000003,
712 HVMSG_GPA_ATTRIBUTE_INTERCEPT = 0x80000004,
713
714 /* Timer notification messages. */
715 HVMSG_TIMER_EXPIRED = 0x80000010,
716
717 /* Error messages. */
718 HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
719 HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
720 HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
721
722 /*
723 * Opaque intercept message. The original intercept message is only
724 * accessible from the mapped intercept message page.
725 */
726 HVMSG_OPAQUE_INTERCEPT = 0x8000003F,
727
728 /* Trace buffer complete messages. */
729 HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
730
731 /* Hypercall intercept */
732 HVMSG_HYPERCALL_INTERCEPT = 0x80000050,
733
734 /* SynIC intercepts */
735 HVMSG_SYNIC_EVENT_INTERCEPT = 0x80000060,
736 HVMSG_SYNIC_SINT_INTERCEPT = 0x80000061,
737 HVMSG_SYNIC_SINT_DELIVERABLE = 0x80000062,
738
739 /* Async call completion intercept */
740 HVMSG_ASYNC_CALL_COMPLETION = 0x80000070,
741
742 /* Root scheduler messages */
743 HVMSG_SCHEDULER_VP_SIGNAL_BITSE = 0x80000100,
744 HVMSG_SCHEDULER_VP_SIGNAL_PAIR = 0x80000101,
745
746 /* Platform-specific processor intercept messages. */
747 HVMSG_X64_IO_PORT_INTERCEPT = 0x80010000,
748 HVMSG_X64_MSR_INTERCEPT = 0x80010001,
749 HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
750 HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
751 HVMSG_X64_APIC_EOI = 0x80010004,
752 HVMSG_X64_LEGACY_FP_ERROR = 0x80010005,
753 HVMSG_X64_IOMMU_PRQ = 0x80010006,
754 HVMSG_X64_HALT = 0x80010007,
755 HVMSG_X64_INTERRUPTION_DELIVERABLE = 0x80010008,
756 HVMSG_X64_SIPI_INTERCEPT = 0x80010009,
757 HVMSG_X64_SEV_VMGEXIT_INTERCEPT = 0x80010013,
758 };
759
760 union hv_x64_vp_execution_state {
761 uint16_t as_uint16;
762 struct {
763 uint16_t cpl:2;
764 uint16_t cr0_pe:1;
765 uint16_t cr0_am:1;
766 uint16_t efer_lma:1;
767 uint16_t debug_active:1;
768 uint16_t interruption_pending:1;
769 uint16_t vtl:4;
770 uint16_t enclave_mode:1;
771 uint16_t interrupt_shadow:1;
772 uint16_t virtualization_fault_active:1;
773 uint16_t reserved:2;
774 };
775 };
776
777 /* From openvmm::hvdef */
778 enum hv_x64_intercept_access_type {
779 HV_X64_INTERCEPT_ACCESS_TYPE_READ = 0,
780 HV_X64_INTERCEPT_ACCESS_TYPE_WRITE = 1,
781 HV_X64_INTERCEPT_ACCESS_TYPE_EXECUTE = 2,
782 };
783
784 struct hv_x64_intercept_message_header {
785 uint32_t vp_index;
786 uint8_t instruction_length:4;
787 uint8_t cr8:4; /* Only set for exo partitions */
788 uint8_t intercept_access_type;
789 union hv_x64_vp_execution_state execution_state;
790 struct hv_x64_segment_register cs_segment;
791 uint64_t rip;
792 uint64_t rflags;
793 } QEMU_PACKED;
794
795 union hv_x64_io_port_access_info {
796 uint8_t as_uint8;
797 struct {
798 uint8_t access_size:3;
799 uint8_t string_op:1;
800 uint8_t rep_prefix:1;
801 uint8_t reserved:3;
802 };
803 };
804
805 typedef struct hv_x64_io_port_intercept_message {
806 struct hv_x64_intercept_message_header header;
807 uint16_t port_number;
808 union hv_x64_io_port_access_info access_info;
809 uint8_t instruction_byte_count;
810 uint32_t reserved;
811 uint64_t rax;
812 uint8_t instruction_bytes[16];
813 struct hv_x64_segment_register ds_segment;
814 struct hv_x64_segment_register es_segment;
815 uint64_t rcx;
816 uint64_t rsi;
817 uint64_t rdi;
818 } QEMU_PACKED hv_x64_io_port_intercept_message;
819
820 union hv_x64_memory_access_info {
821 uint8_t as_uint8;
822 struct {
823 uint8_t gva_valid:1;
824 uint8_t gva_gpa_valid:1;
825 uint8_t hypercall_output_pending:1;
826 uint8_t tlb_locked_no_overlay:1;
827 uint8_t reserved:4;
828 };
829 };
830
831 struct hv_x64_memory_intercept_message {
832 struct hv_x64_intercept_message_header header;
833 uint32_t cache_type; /* enum hv_cache_type */
834 uint8_t instruction_byte_count;
835 union hv_x64_memory_access_info memory_access_info;
836 uint8_t tpr_priority;
837 uint8_t reserved1;
838 uint64_t guest_virtual_address;
839 uint64_t guest_physical_address;
840 uint8_t instruction_bytes[16];
841 } QEMU_PACKED;
842
843 union hv_message_flags {
844 uint8_t asu8;
845 struct {
846 uint8_t msg_pending:1;
847 uint8_t reserved:7;
848 };
849 };
850
851 struct hv_message_header {
852 uint32_t message_type;
853 uint8_t payload_size;
854 union hv_message_flags message_flags;
855 uint8_t reserved[2];
856 union {
857 uint64_t sender;
858 union hv_port_id port;
859 };
860 } QEMU_PACKED;
861
862 struct hv_message {
863 struct hv_message_header header;
864 union {
865 uint64_t payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
866 } u;
867 } QEMU_PACKED;
868
869 /* From github.com/rust-vmm/mshv-bindings/src/x86_64/regs.rs */
870
871 struct hv_cpuid_entry {
872 uint32_t function;
873 uint32_t index;
874 uint32_t flags;
875 uint32_t eax;
876 uint32_t ebx;
877 uint32_t ecx;
878 uint32_t edx;
879 uint32_t padding[3];
880 } QEMU_PACKED;
881
882 struct hv_cpuid {
883 uint32_t nent;
884 uint32_t padding;
885 struct hv_cpuid_entry entries[0];
886 } QEMU_PACKED;
887
888 #define IA32_MSR_TSC 0x00000010
889 #define IA32_MSR_EFER 0xC0000080
890 #define IA32_MSR_KERNEL_GS_BASE 0xC0000102
891 #define IA32_MSR_APIC_BASE 0x0000001B
892 #define IA32_MSR_PAT 0x0277
893 #define IA32_MSR_SYSENTER_CS 0x00000174
894 #define IA32_MSR_SYSENTER_ESP 0x00000175
895 #define IA32_MSR_SYSENTER_EIP 0x00000176
896 #define IA32_MSR_STAR 0xC0000081
897 #define IA32_MSR_LSTAR 0xC0000082
898 #define IA32_MSR_CSTAR 0xC0000083
899 #define IA32_MSR_SFMASK 0xC0000084
900
901 #define IA32_MSR_MTRR_CAP 0x00FE
902 #define IA32_MSR_MTRR_DEF_TYPE 0x02FF
903 #define IA32_MSR_MTRR_PHYSBASE0 0x0200
904 #define IA32_MSR_MTRR_PHYSMASK0 0x0201
905 #define IA32_MSR_MTRR_PHYSBASE1 0x0202
906 #define IA32_MSR_MTRR_PHYSMASK1 0x0203
907 #define IA32_MSR_MTRR_PHYSBASE2 0x0204
908 #define IA32_MSR_MTRR_PHYSMASK2 0x0205
909 #define IA32_MSR_MTRR_PHYSBASE3 0x0206
910 #define IA32_MSR_MTRR_PHYSMASK3 0x0207
911 #define IA32_MSR_MTRR_PHYSBASE4 0x0208
912 #define IA32_MSR_MTRR_PHYSMASK4 0x0209
913 #define IA32_MSR_MTRR_PHYSBASE5 0x020A
914 #define IA32_MSR_MTRR_PHYSMASK5 0x020B
915 #define IA32_MSR_MTRR_PHYSBASE6 0x020C
916 #define IA32_MSR_MTRR_PHYSMASK6 0x020D
917 #define IA32_MSR_MTRR_PHYSBASE7 0x020E
918 #define IA32_MSR_MTRR_PHYSMASK7 0x020F
919
920 #define IA32_MSR_MTRR_FIX64K_00000 0x0250
921 #define IA32_MSR_MTRR_FIX16K_80000 0x0258
922 #define IA32_MSR_MTRR_FIX16K_A0000 0x0259
923 #define IA32_MSR_MTRR_FIX4K_C0000 0x0268
924 #define IA32_MSR_MTRR_FIX4K_C8000 0x0269
925 #define IA32_MSR_MTRR_FIX4K_D0000 0x026A
926 #define IA32_MSR_MTRR_FIX4K_D8000 0x026B
927 #define IA32_MSR_MTRR_FIX4K_E0000 0x026C
928 #define IA32_MSR_MTRR_FIX4K_E8000 0x026D
929 #define IA32_MSR_MTRR_FIX4K_F0000 0x026E
930 #define IA32_MSR_MTRR_FIX4K_F8000 0x026F
931
932 #define IA32_MSR_TSC_AUX 0xC0000103
933 #define IA32_MSR_BNDCFGS 0x00000d90
934 #define IA32_MSR_DEBUG_CTL 0x1D9
935 #define IA32_MSR_SPEC_CTRL 0x00000048
936 #define IA32_MSR_TSC_ADJUST 0x0000003b
937 #define IA32_MSR_TSC_DEADLINE 0x000006e0
938
939 #define IA32_MSR_MISC_ENABLE 0x000001a0
940
941 #define HV_TRANSLATE_GVA_VALIDATE_READ (0x0001)
942 #define HV_TRANSLATE_GVA_VALIDATE_WRITE (0x0002)
943 #define HV_TRANSLATE_GVA_VALIDATE_EXECUTE (0x0004)
944
945 #define HV_HYP_PAGE_SHIFT 12
946 #define HV_HYP_PAGE_SIZE BIT(HV_HYP_PAGE_SHIFT)
947 #define HV_HYP_PAGE_MASK (~(HV_HYP_PAGE_SIZE - 1))
948
949 #define HVCALL_GET_PARTITION_PROPERTY 0x0044
950 #define HVCALL_SET_PARTITION_PROPERTY 0x0045
951 #define HVCALL_GET_VP_REGISTERS 0x0050
952 #define HVCALL_SET_VP_REGISTERS 0x0051
953 #define HVCALL_TRANSLATE_VIRTUAL_ADDRESS 0x0052
954 #define HVCALL_REGISTER_INTERCEPT_RESULT 0x0091
955 #define HVCALL_ASSERT_VIRTUAL_INTERRUPT 0x0094
956
957 #endif /* HW_HYPERV_HVGDK_MINI_H */