| 1 | /* |
| 2 | * Type definitions for the mshv host. |
| 3 | * |
| 4 | * Copyright Microsoft, Corp. 2025 |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef HW_HYPERV_HVHDK_H |
| 10 | #define HW_HYPERV_HVHDK_H |
| 11 | |
| 12 | #define HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS 1 |
| 13 | |
| 14 | struct hv_input_get_partition_property { |
| 15 | uint64_t partition_id; |
| 16 | uint32_t property_code; /* enum hv_partition_property_code */ |
| 17 | uint32_t padding; |
| 18 | } QEMU_PACKED; |
| 19 | |
| 20 | struct hv_output_get_partition_property { |
| 21 | uint64_t property_value; |
| 22 | } QEMU_PACKED; |
| 23 | |
| 24 | struct hv_input_set_partition_property { |
| 25 | uint64_t partition_id; |
| 26 | uint32_t property_code; /* enum hv_partition_property_code */ |
| 27 | uint32_t padding; |
| 28 | uint64_t property_value; |
| 29 | } QEMU_PACKED; |
| 30 | |
| 31 | union hv_partition_synthetic_processor_features { |
| 32 | uint64_t as_uint64[HV_PARTITION_SYNTHETIC_PROCESSOR_FEATURES_BANKS]; |
| 33 | |
| 34 | struct { |
| 35 | /* |
| 36 | * Report a hypervisor is present. CPUID leaves |
| 37 | * 0x40000000 and 0x40000001 are supported. |
| 38 | */ |
| 39 | uint64_t hypervisor_present:1; |
| 40 | |
| 41 | /* |
| 42 | * Features associated with HV#1: |
| 43 | */ |
| 44 | |
| 45 | /* Report support for Hv1 (CPUID leaves 0x40000000 - 0x40000006). */ |
| 46 | uint64_t hv1:1; |
| 47 | |
| 48 | /* |
| 49 | * Access to HV_X64_MSR_VP_RUNTIME. |
| 50 | * Corresponds to access_vp_run_time_reg privilege. |
| 51 | */ |
| 52 | uint64_t access_vp_run_time_reg:1; |
| 53 | |
| 54 | /* |
| 55 | * Access to HV_X64_MSR_TIME_REF_COUNT. |
| 56 | * Corresponds to access_partition_reference_counter privilege. |
| 57 | */ |
| 58 | uint64_t access_partition_reference_counter:1; |
| 59 | |
| 60 | /* |
| 61 | * Access to SINT-related registers (HV_X64_MSR_SCONTROL through |
| 62 | * HV_X64_MSR_EOM and HV_X64_MSR_SINT0 through HV_X64_MSR_SINT15). |
| 63 | * Corresponds to access_synic_regs privilege. |
| 64 | */ |
| 65 | uint64_t access_synic_regs:1; |
| 66 | |
| 67 | /* |
| 68 | * Access to synthetic timers and associated MSRs |
| 69 | * (HV_X64_MSR_STIMER0_CONFIG through HV_X64_MSR_STIMER3_COUNT). |
| 70 | * Corresponds to access_synthetic_timer_regs privilege. |
| 71 | */ |
| 72 | uint64_t access_synthetic_timer_regs:1; |
| 73 | |
| 74 | /* |
| 75 | * Access to APIC MSRs (HV_X64_MSR_EOI, HV_X64_MSR_ICR and |
| 76 | * HV_X64_MSR_TPR) as well as the VP assist page. |
| 77 | * Corresponds to access_intr_ctrl_regs privilege. |
| 78 | */ |
| 79 | uint64_t access_intr_ctrl_regs:1; |
| 80 | |
| 81 | /* |
| 82 | * Access to registers associated with hypercalls |
| 83 | * (HV_X64_MSR_GUEST_OS_ID and HV_X64_MSR_HYPERCALL). |
| 84 | * Corresponds to access_hypercall_msrs privilege. |
| 85 | */ |
| 86 | uint64_t access_hypercall_regs:1; |
| 87 | |
| 88 | /* VP index can be queried. corresponds to access_vp_index privilege. */ |
| 89 | uint64_t access_vp_index:1; |
| 90 | |
| 91 | /* |
| 92 | * Access to the reference TSC. Corresponds to |
| 93 | * access_partition_reference_tsc privilege. |
| 94 | */ |
| 95 | uint64_t access_partition_reference_tsc:1; |
| 96 | |
| 97 | /* |
| 98 | * Partition has access to the guest idle reg. Corresponds to |
| 99 | * access_guest_idle_reg privilege. |
| 100 | */ |
| 101 | uint64_t access_guest_idle_reg:1; |
| 102 | |
| 103 | /* |
| 104 | * Partition has access to frequency regs. corresponds to |
| 105 | * access_frequency_regs privilege. |
| 106 | */ |
| 107 | uint64_t access_frequency_regs:1; |
| 108 | |
| 109 | uint64_t reserved_z12:1; /* Reserved for access_reenlightenment_controls */ |
| 110 | uint64_t reserved_z13:1; /* Reserved for access_root_scheduler_reg */ |
| 111 | uint64_t reserved_z14:1; /* Reserved for access_tsc_invariant_controls */ |
| 112 | |
| 113 | /* |
| 114 | * Extended GVA ranges for HvCallFlushVirtualAddressList hypercall. |
| 115 | * Corresponds to privilege. |
| 116 | */ |
| 117 | uint64_t enable_extended_gva_ranges_for_flush_virtual_address_list:1; |
| 118 | |
| 119 | uint64_t reserved_z16:1; /* Reserved for access_vsm. */ |
| 120 | uint64_t reserved_z17:1; /* Reserved for access_vp_registers. */ |
| 121 | |
| 122 | /* Use fast hypercall output. Corresponds to privilege. */ |
| 123 | uint64_t fast_hypercall_output:1; |
| 124 | |
| 125 | uint64_t reserved_z19:1; /* Reserved for enable_extended_hypercalls. */ |
| 126 | |
| 127 | /* |
| 128 | * HvStartVirtualProcessor can be used to start virtual processors. |
| 129 | * Corresponds to privilege. |
| 130 | */ |
| 131 | uint64_t start_virtual_processor:1; |
| 132 | |
| 133 | uint64_t reserved_z21:1; /* Reserved for Isolation. */ |
| 134 | |
| 135 | /* Synthetic timers in direct mode. */ |
| 136 | uint64_t direct_synthetic_timers:1; |
| 137 | |
| 138 | uint64_t reserved_z23:1; /* Reserved for synthetic time unhalted timer */ |
| 139 | |
| 140 | /* Use extended processor masks. */ |
| 141 | uint64_t extended_processor_masks:1; |
| 142 | |
| 143 | /* |
| 144 | * HvCallFlushVirtualAddressSpace / HvCallFlushVirtualAddressList are |
| 145 | * supported. |
| 146 | */ |
| 147 | uint64_t tb_flush_hypercalls:1; |
| 148 | |
| 149 | /* HvCallSendSyntheticClusterIpi is supported. */ |
| 150 | uint64_t synthetic_cluster_ipi:1; |
| 151 | |
| 152 | /* HvCallNotifyLongSpinWait is supported. */ |
| 153 | uint64_t notify_long_spin_wait:1; |
| 154 | |
| 155 | /* HvCallQueryNumaDistance is supported. */ |
| 156 | uint64_t query_numa_distance:1; |
| 157 | |
| 158 | /* HvCallSignalEvent is supported. Corresponds to privilege. */ |
| 159 | uint64_t signal_events:1; |
| 160 | |
| 161 | /* HvCallRetargetDeviceInterrupt is supported. */ |
| 162 | uint64_t retarget_device_interrupt:1; |
| 163 | |
| 164 | /* HvCallRestorePartitionTime is supported. */ |
| 165 | uint64_t restore_time:1; |
| 166 | |
| 167 | /* EnlightenedVmcs nested enlightenment is supported. */ |
| 168 | uint64_t enlightened_vmcs:1; |
| 169 | |
| 170 | uint64_t reserved:30; |
| 171 | }; |
| 172 | }; |
| 173 | |
| 174 | union hv_partition_processor_xsave_features { |
| 175 | struct { |
| 176 | uint64_t xsave_support:1; |
| 177 | uint64_t xsaveopt_support:1; |
| 178 | uint64_t avx_support:1; |
| 179 | uint64_t avx2_support:1; |
| 180 | uint64_t fma_support:1; |
| 181 | uint64_t mpx_support:1; |
| 182 | uint64_t avx512_support:1; |
| 183 | uint64_t avx512_dq_support:1; |
| 184 | uint64_t avx512_cd_support:1; |
| 185 | uint64_t avx512_bw_support:1; |
| 186 | uint64_t avx512_vl_support:1; |
| 187 | uint64_t xsave_comp_support:1; |
| 188 | uint64_t xsave_supervisor_support:1; |
| 189 | uint64_t xcr1_support:1; |
| 190 | uint64_t avx512_bitalg_support:1; |
| 191 | uint64_t avx512_i_fma_support:1; |
| 192 | uint64_t avx512_v_bmi_support:1; |
| 193 | uint64_t avx512_v_bmi2_support:1; |
| 194 | uint64_t avx512_vnni_support:1; |
| 195 | uint64_t gfni_support:1; |
| 196 | uint64_t vaes_support:1; |
| 197 | uint64_t avx512_v_popcntdq_support:1; |
| 198 | uint64_t vpclmulqdq_support:1; |
| 199 | uint64_t avx512_bf16_support:1; |
| 200 | uint64_t avx512_vp2_intersect_support:1; |
| 201 | uint64_t avx512_fp16_support:1; |
| 202 | uint64_t xfd_support:1; |
| 203 | uint64_t amx_tile_support:1; |
| 204 | uint64_t amx_bf16_support:1; |
| 205 | uint64_t amx_int8_support:1; |
| 206 | uint64_t avx_vnni_support:1; |
| 207 | uint64_t avx_ifma_support:1; |
| 208 | uint64_t avx_ne_convert_support:1; |
| 209 | uint64_t avx_vnni_int8_support:1; |
| 210 | uint64_t avx_vnni_int16_support:1; |
| 211 | uint64_t avx10_1_256_support:1; |
| 212 | uint64_t avx10_1_512_support:1; |
| 213 | uint64_t amx_fp16_support:1; |
| 214 | uint64_t reserved1:26; |
| 215 | }; |
| 216 | uint64_t as_uint64; |
| 217 | }; |
| 218 | |
| 219 | #define HV_PARTITION_PROCESSOR_FEATURES_BANKS 2 |
| 220 | #define HV_PARTITION_PROCESSOR_FEATURES_RESERVEDBANK1_BITFIELD_COUNT 4 |
| 221 | |
| 222 | |
| 223 | union hv_partition_processor_features { |
| 224 | uint64_t as_uint64[HV_PARTITION_PROCESSOR_FEATURES_BANKS]; |
| 225 | struct { |
| 226 | uint64_t sse3_support:1; |
| 227 | uint64_t lahf_sahf_support:1; |
| 228 | uint64_t ssse3_support:1; |
| 229 | uint64_t sse4_1_support:1; |
| 230 | uint64_t sse4_2_support:1; |
| 231 | uint64_t sse4a_support:1; |
| 232 | uint64_t xop_support:1; |
| 233 | uint64_t pop_cnt_support:1; |
| 234 | uint64_t cmpxchg16b_support:1; |
| 235 | uint64_t altmovcr8_support:1; |
| 236 | uint64_t lzcnt_support:1; |
| 237 | uint64_t mis_align_sse_support:1; |
| 238 | uint64_t mmx_ext_support:1; |
| 239 | uint64_t amd3dnow_support:1; |
| 240 | uint64_t extended_amd3dnow_support:1; |
| 241 | uint64_t page_1gb_support:1; |
| 242 | uint64_t aes_support:1; |
| 243 | uint64_t pclmulqdq_support:1; |
| 244 | uint64_t pcid_support:1; |
| 245 | uint64_t fma4_support:1; |
| 246 | uint64_t f16c_support:1; |
| 247 | uint64_t rd_rand_support:1; |
| 248 | uint64_t rd_wr_fs_gs_support:1; |
| 249 | uint64_t smep_support:1; |
| 250 | uint64_t enhanced_fast_string_support:1; |
| 251 | uint64_t bmi1_support:1; |
| 252 | uint64_t bmi2_support:1; |
| 253 | uint64_t hle_support_deprecated:1; |
| 254 | uint64_t rtm_support_deprecated:1; |
| 255 | uint64_t movbe_support:1; |
| 256 | uint64_t npiep1_support:1; |
| 257 | uint64_t dep_x87_fpu_save_support:1; |
| 258 | uint64_t rd_seed_support:1; |
| 259 | uint64_t adx_support:1; |
| 260 | uint64_t intel_prefetch_support:1; |
| 261 | uint64_t smap_support:1; |
| 262 | uint64_t hle_support:1; |
| 263 | uint64_t rtm_support:1; |
| 264 | uint64_t rdtscp_support:1; |
| 265 | uint64_t clflushopt_support:1; |
| 266 | uint64_t clwb_support:1; |
| 267 | uint64_t sha_support:1; |
| 268 | uint64_t x87_pointers_saved_support:1; |
| 269 | uint64_t invpcid_support:1; |
| 270 | uint64_t ibrs_support:1; |
| 271 | uint64_t stibp_support:1; |
| 272 | uint64_t ibpb_support:1; |
| 273 | uint64_t unrestricted_guest_support:1; |
| 274 | uint64_t mdd_support:1; |
| 275 | uint64_t fast_short_rep_mov_support:1; |
| 276 | uint64_t l1dcache_flush_support:1; |
| 277 | uint64_t rdcl_no_support:1; |
| 278 | uint64_t ibrs_all_support:1; |
| 279 | uint64_t skip_l1df_support:1; |
| 280 | uint64_t ssb_no_support:1; |
| 281 | uint64_t rsb_a_no_support:1; |
| 282 | uint64_t virt_spec_ctrl_support:1; |
| 283 | uint64_t rd_pid_support:1; |
| 284 | uint64_t umip_support:1; |
| 285 | uint64_t mbs_no_support:1; |
| 286 | uint64_t mb_clear_support:1; |
| 287 | uint64_t taa_no_support:1; |
| 288 | uint64_t tsx_ctrl_support:1; |
| 289 | uint64_t reserved_bank0:1; |
| 290 | |
| 291 | /* N.B. Begin bank 1 processor features. */ |
| 292 | uint64_t a_count_m_count_support:1; |
| 293 | uint64_t tsc_invariant_support:1; |
| 294 | uint64_t cl_zero_support:1; |
| 295 | uint64_t rdpru_support:1; |
| 296 | uint64_t la57_support:1; |
| 297 | uint64_t mbec_support:1; |
| 298 | uint64_t nested_virt_support:1; |
| 299 | uint64_t psfd_support:1; |
| 300 | uint64_t cet_ss_support:1; |
| 301 | uint64_t cet_ibt_support:1; |
| 302 | uint64_t vmx_exception_inject_support:1; |
| 303 | uint64_t enqcmd_support:1; |
| 304 | uint64_t umwait_tpause_support:1; |
| 305 | uint64_t movdiri_support:1; |
| 306 | uint64_t movdir64b_support:1; |
| 307 | uint64_t cldemote_support:1; |
| 308 | uint64_t serialize_support:1; |
| 309 | uint64_t tsc_deadline_tmr_support:1; |
| 310 | uint64_t tsc_adjust_support:1; |
| 311 | uint64_t fzl_rep_movsb:1; |
| 312 | uint64_t fs_rep_stosb:1; |
| 313 | uint64_t fs_rep_cmpsb:1; |
| 314 | uint64_t tsx_ld_trk_support:1; |
| 315 | uint64_t vmx_ins_outs_exit_info_support:1; |
| 316 | uint64_t hlat_support:1; |
| 317 | uint64_t sbdr_ssdp_no_support:1; |
| 318 | uint64_t fbsdp_no_support:1; |
| 319 | uint64_t psdp_no_support:1; |
| 320 | uint64_t fb_clear_support:1; |
| 321 | uint64_t btc_no_support:1; |
| 322 | uint64_t ibpb_rsb_flush_support:1; |
| 323 | uint64_t stibp_always_on_support:1; |
| 324 | uint64_t perf_global_ctrl_support:1; |
| 325 | uint64_t npt_execute_only_support:1; |
| 326 | uint64_t npt_ad_flags_support:1; |
| 327 | uint64_t npt1_gb_page_support:1; |
| 328 | uint64_t amd_processor_topology_node_id_support:1; |
| 329 | uint64_t local_machine_check_support:1; |
| 330 | uint64_t extended_topology_leaf_fp256_amd_support:1; |
| 331 | uint64_t gds_no_support:1; |
| 332 | uint64_t cmpccxadd_support:1; |
| 333 | uint64_t tsc_aux_virtualization_support:1; |
| 334 | uint64_t rmp_query_support:1; |
| 335 | uint64_t bhi_no_support:1; |
| 336 | uint64_t bhi_dis_support:1; |
| 337 | uint64_t prefetch_i_support:1; |
| 338 | uint64_t sha512_support:1; |
| 339 | uint64_t mitigation_ctrl_support:1; |
| 340 | uint64_t rfds_no_support:1; |
| 341 | uint64_t rfds_clear_support:1; |
| 342 | uint64_t sm3_support:1; |
| 343 | uint64_t sm4_support:1; |
| 344 | uint64_t secure_avic_support:1; |
| 345 | uint64_t guest_intercept_ctrl_support:1; |
| 346 | uint64_t sbpb_supported:1; |
| 347 | uint64_t ibpb_br_type_supported:1; |
| 348 | uint64_t srso_no_supported:1; |
| 349 | uint64_t srso_user_kernel_no_supported:1; |
| 350 | uint64_t vrew_clear_supported:1; |
| 351 | uint64_t tsa_l1_no_supported:1; |
| 352 | uint64_t tsa_sq_no_supported:1; |
| 353 | uint64_t lass_support:1; |
| 354 | uint64_t idle_hlt_intercept_support:1; |
| 355 | uint64_t msr_list_support:1; |
| 356 | } QEMU_PACKED; |
| 357 | }; |
| 358 | |
| 359 | enum hv_translate_gva_result_code { |
| 360 | HV_TRANSLATE_GVA_SUCCESS = 0, |
| 361 | |
| 362 | /* Translation failures. */ |
| 363 | HV_TRANSLATE_GVA_PAGE_NOT_PRESENT = 1, |
| 364 | HV_TRANSLATE_GVA_PRIVILEGE_VIOLATION = 2, |
| 365 | HV_TRANSLATE_GVA_INVALIDE_PAGE_TABLE_FLAGS = 3, |
| 366 | |
| 367 | /* GPA access failures. */ |
| 368 | HV_TRANSLATE_GVA_GPA_UNMAPPED = 4, |
| 369 | HV_TRANSLATE_GVA_GPA_NO_READ_ACCESS = 5, |
| 370 | HV_TRANSLATE_GVA_GPA_NO_WRITE_ACCESS = 6, |
| 371 | HV_TRANSLATE_GVA_GPA_ILLEGAL_OVERLAY_ACCESS = 7, |
| 372 | |
| 373 | /* |
| 374 | * Intercept for memory access by either |
| 375 | * - a higher VTL |
| 376 | * - a nested hypervisor (due to a violation of the nested page table) |
| 377 | */ |
| 378 | HV_TRANSLATE_GVA_INTERCEPT = 8, |
| 379 | |
| 380 | HV_TRANSLATE_GVA_GPA_UNACCEPTED = 9, |
| 381 | }; |
| 382 | |
| 383 | union hv_translate_gva_result { |
| 384 | uint64_t as_uint64; |
| 385 | struct { |
| 386 | uint32_t result_code; /* enum hv_translate_hva_result_code */ |
| 387 | uint32_t cache_type:8; |
| 388 | uint32_t overlay_page:1; |
| 389 | uint32_t reserved:23; |
| 390 | }; |
| 391 | }; |
| 392 | |
| 393 | typedef struct hv_input_translate_virtual_address { |
| 394 | uint64_t partition_id; |
| 395 | uint32_t vp_index; |
| 396 | uint32_t padding; |
| 397 | uint64_t control_flags; |
| 398 | uint64_t gva_page; |
| 399 | } QEMU_PACKED hv_input_translate_virtual_address; |
| 400 | |
| 401 | typedef struct hv_output_translate_virtual_address { |
| 402 | union hv_translate_gva_result translation_result; |
| 403 | uint64_t gpa_page; |
| 404 | } QEMU_PACKED hv_output_translate_virtual_address; |
| 405 | |
| 406 | typedef struct hv_register_x64_cpuid_result_parameters { |
| 407 | struct { |
| 408 | uint32_t eax; |
| 409 | uint32_t ecx; |
| 410 | uint8_t subleaf_specific; |
| 411 | uint8_t always_override; |
| 412 | uint16_t padding; |
| 413 | } input; |
| 414 | struct { |
| 415 | uint32_t eax; |
| 416 | uint32_t eax_mask; |
| 417 | uint32_t ebx; |
| 418 | uint32_t ebx_mask; |
| 419 | uint32_t ecx; |
| 420 | uint32_t ecx_mask; |
| 421 | uint32_t edx; |
| 422 | uint32_t edx_mask; |
| 423 | } result; |
| 424 | } QEMU_PACKED hv_register_x64_cpuid_result_parameters; |
| 425 | |
| 426 | typedef struct hv_register_x64_msr_result_parameters { |
| 427 | uint32_t msr_index; |
| 428 | uint32_t access_type; |
| 429 | uint32_t action; /* enum hv_unimplemented_msr_action */ |
| 430 | } QEMU_PACKED hv_register_x64_msr_result_parameters; |
| 431 | |
| 432 | union hv_register_intercept_result_parameters { |
| 433 | struct hv_register_x64_cpuid_result_parameters cpuid; |
| 434 | struct hv_register_x64_msr_result_parameters msr; |
| 435 | }; |
| 436 | |
| 437 | typedef struct hv_input_register_intercept_result { |
| 438 | uint64_t partition_id; |
| 439 | uint32_t vp_index; |
| 440 | uint32_t intercept_type; /* enum hv_intercept_type */ |
| 441 | union hv_register_intercept_result_parameters parameters; |
| 442 | } QEMU_PACKED hv_input_register_intercept_result; |
| 443 | |
| 444 | #endif /* HW_HYPERV_HVHDK_H */ |