| 1 | /* |
| 2 | * ASPEED AST2400 I2C Controller |
| 3 | * |
| 4 | * Copyright (C) 2016 IBM Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License along |
| 17 | * with this program; if not, see <https://www.gnu.org/licenses/>. |
| 18 | */ |
| 19 | |
| 20 | #ifndef ASPEED_I2C_H |
| 21 | #define ASPEED_I2C_H |
| 22 | |
| 23 | #include "hw/i2c/i2c.h" |
| 24 | #include "hw/core/sysbus.h" |
| 25 | #include "hw/core/registerfields.h" |
| 26 | #include "qom/object.h" |
| 27 | |
| 28 | #define TYPE_ASPEED_I2C "aspeed.i2c" |
| 29 | #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" |
| 30 | #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" |
| 31 | #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" |
| 32 | #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030" |
| 33 | #define TYPE_ASPEED_1040_I2C TYPE_ASPEED_I2C "-ast1040" |
| 34 | #define TYPE_ASPEED_2700_I2C TYPE_ASPEED_I2C "-ast2700" |
| 35 | OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) |
| 36 | |
| 37 | #define ASPEED_I2C_NR_BUSSES 16 |
| 38 | #define ASPEED_I2C_SHARE_POOL_SIZE 0x800 |
| 39 | #define ASPEED_I2C_BUS_POOL_SIZE 0x40 |
| 40 | #define ASPEED_I2C_NEW_NUM_REG (0xa0 >> 2) |
| 41 | |
| 42 | #define A_I2CD_M_STOP_CMD BIT(5) |
| 43 | #define A_I2CD_M_RX_CMD BIT(3) |
| 44 | #define A_I2CD_M_TX_CMD BIT(1) |
| 45 | #define A_I2CD_M_START_CMD BIT(0) |
| 46 | |
| 47 | #define A_I2CD_MASTER_EN BIT(0) |
| 48 | |
| 49 | /* Tx State Machine */ |
| 50 | #define I2CD_TX_STATE_MASK 0xf |
| 51 | #define I2CD_IDLE 0x0 |
| 52 | #define I2CD_MACTIVE 0x8 |
| 53 | #define I2CD_MSTART 0x9 |
| 54 | #define I2CD_MSTARTR 0xa |
| 55 | #define I2CD_MSTOP 0xb |
| 56 | #define I2CD_MTXD 0xc |
| 57 | #define I2CD_MRXACK 0xd |
| 58 | #define I2CD_MRXD 0xe |
| 59 | #define I2CD_MTXACK 0xf |
| 60 | #define I2CD_SWAIT 0x1 |
| 61 | #define I2CD_SRXD 0x4 |
| 62 | #define I2CD_STXACK 0x5 |
| 63 | #define I2CD_STXD 0x6 |
| 64 | #define I2CD_SRXACK 0x7 |
| 65 | #define I2CD_RECOVER 0x3 |
| 66 | |
| 67 | /* I2C Global Register */ |
| 68 | REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */ |
| 69 | REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */ |
| 70 | REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */ |
| 71 | FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1) |
| 72 | FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1) |
| 73 | REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */ |
| 74 | |
| 75 | /* I2C Old Mode Device (Bus) Register */ |
| 76 | REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */ |
| 77 | FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */ |
| 78 | SHARED_FIELD(M_SDA_LOCK_EN, 16, 1) |
| 79 | SHARED_FIELD(MULTI_MASTER_DIS, 15, 1) |
| 80 | SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1) |
| 81 | SHARED_FIELD(MSB_STS, 9, 1) |
| 82 | SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1) |
| 83 | SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1) |
| 84 | SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1) |
| 85 | SHARED_FIELD(DEF_ADDR_EN, 5, 1) |
| 86 | SHARED_FIELD(DEF_ALERT_EN, 4, 1) |
| 87 | SHARED_FIELD(DEF_ARP_EN, 3, 1) |
| 88 | SHARED_FIELD(DEF_GCALL_EN, 2, 1) |
| 89 | SHARED_FIELD(SLAVE_EN, 1, 1) |
| 90 | SHARED_FIELD(MASTER_EN, 0, 1) |
| 91 | REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */ |
| 92 | REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */ |
| 93 | REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */ |
| 94 | REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */ |
| 95 | SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */ |
| 96 | SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1) |
| 97 | SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1) |
| 98 | SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1) |
| 99 | SHARED_FIELD(BUS_RECOVER_DONE, 13, 1) |
| 100 | SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */ |
| 101 | FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */ |
| 102 | FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */ |
| 103 | FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */ |
| 104 | FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */ |
| 105 | FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */ |
| 106 | SHARED_FIELD(SCL_TIMEOUT, 6, 1) |
| 107 | SHARED_FIELD(ABNORMAL, 5, 1) |
| 108 | SHARED_FIELD(NORMAL_STOP, 4, 1) |
| 109 | SHARED_FIELD(ARBIT_LOSS, 3, 1) |
| 110 | SHARED_FIELD(RX_DONE, 2, 1) |
| 111 | SHARED_FIELD(TX_NAK, 1, 1) |
| 112 | SHARED_FIELD(TX_ACK, 0, 1) |
| 113 | REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ |
| 114 | SHARED_FIELD(SDA_OE, 28, 1) |
| 115 | SHARED_FIELD(SDA_O, 27, 1) |
| 116 | SHARED_FIELD(SCL_OE, 26, 1) |
| 117 | SHARED_FIELD(SCL_O, 25, 1) |
| 118 | SHARED_FIELD(TX_TIMING, 23, 2) |
| 119 | SHARED_FIELD(TX_STATE, 19, 4) |
| 120 | SHARED_FIELD(SCL_LINE_STS, 18, 1) |
| 121 | SHARED_FIELD(SDA_LINE_STS, 17, 1) |
| 122 | SHARED_FIELD(BUS_BUSY_STS, 16, 1) |
| 123 | SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1) |
| 124 | SHARED_FIELD(SDA_O_OUT_DIR, 14, 1) |
| 125 | SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1) |
| 126 | SHARED_FIELD(SCL_O_OUT_DIR, 12, 1) |
| 127 | SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1) |
| 128 | SHARED_FIELD(S_ALT_EN, 10, 1) |
| 129 | /* Command Bits */ |
| 130 | SHARED_FIELD(RX_DMA_EN, 9, 1) |
| 131 | SHARED_FIELD(TX_DMA_EN, 8, 1) |
| 132 | SHARED_FIELD(RX_BUFF_EN, 7, 1) |
| 133 | SHARED_FIELD(TX_BUFF_EN, 6, 1) |
| 134 | SHARED_FIELD(M_STOP_CMD, 5, 1) |
| 135 | SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1) |
| 136 | SHARED_FIELD(M_RX_CMD, 3, 1) |
| 137 | SHARED_FIELD(S_TX_CMD, 2, 1) |
| 138 | SHARED_FIELD(M_TX_CMD, 1, 1) |
| 139 | SHARED_FIELD(M_START_CMD, 0, 1) |
| 140 | REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ |
| 141 | SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7) |
| 142 | REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ |
| 143 | SHARED_FIELD(RX_COUNT, 24, 6) |
| 144 | SHARED_FIELD(RX_SIZE, 16, 5) |
| 145 | SHARED_FIELD(TX_COUNT, 8, 5) |
| 146 | FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ |
| 147 | SHARED_FIELD(BUF_ORGANIZATION, 0, 1) /* AST2600 */ |
| 148 | REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ |
| 149 | SHARED_FIELD(RX_BUF, 8, 8) |
| 150 | SHARED_FIELD(TX_BUF, 0, 8) |
| 151 | REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */ |
| 152 | REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */ |
| 153 | |
| 154 | /* I2C New Mode Device (Bus) Register */ |
| 155 | REG32(I2CC_FUN_CTRL, 0x0) |
| 156 | FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1) |
| 157 | FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1) |
| 158 | FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1) |
| 159 | FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2) |
| 160 | /* 17:0 shared with I2CD_FUN_CTRL[17:0] */ |
| 161 | REG32(I2CC_AC_TIMING, 0x04) |
| 162 | REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08) |
| 163 | /* 31:16 shared with I2CD_CMD[31:16] */ |
| 164 | /* 15:0 shared with I2CD_BYTE_BUF[15:0] */ |
| 165 | REG32(I2CC_POOL_CTRL, 0x0c) |
| 166 | /* 31:0 shared with I2CD_POOL_CTRL[31:0] */ |
| 167 | REG32(I2CM_INTR_CTRL, 0x10) |
| 168 | REG32(I2CM_INTR_STS, 0x14) |
| 169 | FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4) |
| 170 | FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1) |
| 171 | FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1) |
| 172 | FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1) |
| 173 | FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1) |
| 174 | /* 14:0 shared with I2CD_INTR_STS[14:0] */ |
| 175 | REG32(I2CM_CMD, 0x18) |
| 176 | FIELD(I2CM_CMD, W1_CTRL, 31, 1) |
| 177 | FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7) |
| 178 | FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3) |
| 179 | FIELD(I2CM_CMD, PKT_OP_EN, 16, 1) |
| 180 | /* 15:0 shared with I2CD_CMD[15:0] */ |
| 181 | REG32(I2CM_DMA_LEN, 0x1c) |
| 182 | FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) |
| 183 | FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11) |
| 184 | FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) |
| 185 | FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11) |
| 186 | REG32(I2CS_INTR_CTRL, 0x20) |
| 187 | FIELD(I2CS_INTR_CTRL, PKT_CMD_FAIL, 17, 1) |
| 188 | FIELD(I2CS_INTR_CTRL, PKT_CMD_DONE, 16, 1) |
| 189 | REG32(I2CS_INTR_STS, 0x24) |
| 190 | /* 31:29 shared with I2CD_INTR_STS[31:29] */ |
| 191 | FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2) |
| 192 | FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1) |
| 193 | FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1) |
| 194 | FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1) |
| 195 | FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2) |
| 196 | FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1) |
| 197 | FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1) |
| 198 | /* 14:0 shared with I2CD_INTR_STS[14:0] */ |
| 199 | FIELD(I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) |
| 200 | REG32(I2CS_CMD, 0x28) |
| 201 | FIELD(I2CS_CMD, W1_CTRL, 31, 1) |
| 202 | FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2) |
| 203 | FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1) |
| 204 | FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1) |
| 205 | FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1) |
| 206 | /* 13:0 shared with I2CD_CMD[13:0] */ |
| 207 | REG32(I2CS_DMA_LEN, 0x2c) |
| 208 | FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) |
| 209 | FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11) |
| 210 | FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) |
| 211 | FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11) |
| 212 | REG32(I2CM_DMA_TX_ADDR, 0x30) |
| 213 | REG32(I2CM_DMA_RX_ADDR, 0x34) |
| 214 | REG32(I2CS_DMA_TX_ADDR, 0x38) |
| 215 | REG32(I2CS_DMA_RX_ADDR, 0x3c) |
| 216 | REG32(I2CS_DEV_ADDR, 0x40) |
| 217 | REG32(I2CM_DMA_LEN_STS, 0x48) |
| 218 | FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13) |
| 219 | FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13) |
| 220 | REG32(I2CS_DMA_LEN_STS, 0x4c) |
| 221 | FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13) |
| 222 | FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) |
| 223 | REG32(I2CC_DMA_ADDR, 0x50) |
| 224 | REG32(I2CC_DMA_LEN, 0x54) |
| 225 | /* DMA 64bits */ |
| 226 | REG32(I2CM_DMA_TX_ADDR_HI, 0x60) |
| 227 | FIELD(I2CM_DMA_TX_ADDR_HI, ADDR_HI, 0, 7) |
| 228 | REG32(I2CM_DMA_RX_ADDR_HI, 0x64) |
| 229 | FIELD(I2CM_DMA_RX_ADDR_HI, ADDR_HI, 0, 7) |
| 230 | REG32(I2CS_DMA_TX_ADDR_HI, 0x68) |
| 231 | FIELD(I2CS_DMA_TX_ADDR_HI, ADDR_HI, 0, 7) |
| 232 | REG32(I2CS_DMA_RX_ADDR_HI, 0x6c) |
| 233 | FIELD(I2CS_DMA_RX_ADDR_HI, ADDR_HI, 0, 7) |
| 234 | REG32(I2CC_VERSION_CTRL, 0x94) |
| 235 | FIELD(I2CC_VERSION_CTRL, FUNC_CFG_DMA_EN, 2, 1) |
| 236 | |
| 237 | struct AspeedI2CState; |
| 238 | |
| 239 | #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus" |
| 240 | OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS) |
| 241 | struct AspeedI2CBus { |
| 242 | SysBusDevice parent_obj; |
| 243 | |
| 244 | struct AspeedI2CState *controller; |
| 245 | |
| 246 | /* slave mode */ |
| 247 | I2CSlave *slave; |
| 248 | |
| 249 | MemoryRegion mr; |
| 250 | MemoryRegion mr_pool; |
| 251 | |
| 252 | I2CBus *bus; |
| 253 | char *name; |
| 254 | uint8_t id; |
| 255 | qemu_irq irq; |
| 256 | |
| 257 | uint32_t regs[ASPEED_I2C_NEW_NUM_REG]; |
| 258 | uint32_t pending_intr_sts; |
| 259 | uint8_t pool[ASPEED_I2C_BUS_POOL_SIZE]; |
| 260 | uint64_t dma_dram_offset; |
| 261 | }; |
| 262 | |
| 263 | struct AspeedI2CState { |
| 264 | SysBusDevice parent_obj; |
| 265 | |
| 266 | MemoryRegion iomem; |
| 267 | qemu_irq irq; |
| 268 | |
| 269 | uint32_t intr_status; |
| 270 | uint32_t ctrl_global; |
| 271 | uint32_t new_clk_divider; |
| 272 | char *bus_label; |
| 273 | MemoryRegion pool_iomem; |
| 274 | uint8_t share_pool[ASPEED_I2C_SHARE_POOL_SIZE]; |
| 275 | |
| 276 | AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; |
| 277 | MemoryRegion *dram_mr; |
| 278 | AddressSpace dram_as; |
| 279 | }; |
| 280 | |
| 281 | #define TYPE_ASPEED_I2C_BUS_SLAVE "aspeed.i2c.slave" |
| 282 | OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBusSlave, ASPEED_I2C_BUS_SLAVE) |
| 283 | struct AspeedI2CBusSlave { |
| 284 | I2CSlave i2c; |
| 285 | }; |
| 286 | |
| 287 | struct AspeedI2CClass { |
| 288 | SysBusDeviceClass parent_class; |
| 289 | |
| 290 | uint8_t num_busses; |
| 291 | uint8_t reg_size; |
| 292 | uint32_t reg_gap_size; |
| 293 | uint8_t gap; |
| 294 | qemu_irq (*bus_get_irq)(AspeedI2CBus *); |
| 295 | |
| 296 | uint64_t pool_size; |
| 297 | hwaddr pool_base; |
| 298 | uint32_t pool_gap_size; |
| 299 | uint8_t *(*bus_pool_base)(AspeedI2CBus *); |
| 300 | bool check_sram; |
| 301 | bool has_dma; |
| 302 | bool has_share_pool; |
| 303 | uint64_t mem_size; |
| 304 | bool has_dma64; |
| 305 | uint32_t dma_addr_lo_mask; |
| 306 | }; |
| 307 | |
| 308 | static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) |
| 309 | { |
| 310 | return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE); |
| 311 | } |
| 312 | |
| 313 | static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus) |
| 314 | { |
| 315 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 316 | return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN); |
| 317 | } |
| 318 | return false; |
| 319 | } |
| 320 | |
| 321 | static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus) |
| 322 | { |
| 323 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 324 | return R_I2CC_FUN_CTRL; |
| 325 | } |
| 326 | return R_I2CD_FUN_CTRL; |
| 327 | } |
| 328 | |
| 329 | static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus) |
| 330 | { |
| 331 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 332 | return R_I2CM_CMD; |
| 333 | } |
| 334 | return R_I2CD_CMD; |
| 335 | } |
| 336 | |
| 337 | static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus) |
| 338 | { |
| 339 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 340 | return R_I2CS_DEV_ADDR; |
| 341 | } |
| 342 | return R_I2CD_DEV_ADDR; |
| 343 | } |
| 344 | |
| 345 | static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus) |
| 346 | { |
| 347 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 348 | return R_I2CM_INTR_CTRL; |
| 349 | } |
| 350 | return R_I2CD_INTR_CTRL; |
| 351 | } |
| 352 | |
| 353 | static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus) |
| 354 | { |
| 355 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 356 | return R_I2CM_INTR_STS; |
| 357 | } |
| 358 | return R_I2CD_INTR_STS; |
| 359 | } |
| 360 | |
| 361 | static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus) |
| 362 | { |
| 363 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 364 | return R_I2CC_POOL_CTRL; |
| 365 | } |
| 366 | return R_I2CD_POOL_CTRL; |
| 367 | } |
| 368 | |
| 369 | static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus) |
| 370 | { |
| 371 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 372 | return R_I2CC_MS_TXRX_BYTE_BUF; |
| 373 | } |
| 374 | return R_I2CD_BYTE_BUF; |
| 375 | } |
| 376 | |
| 377 | static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus) |
| 378 | { |
| 379 | if (aspeed_i2c_is_new_mode(bus->controller)) { |
| 380 | return R_I2CC_DMA_LEN; |
| 381 | } |
| 382 | return R_I2CD_DMA_LEN; |
| 383 | } |
| 384 | |
| 385 | static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) |
| 386 | { |
| 387 | return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus), |
| 388 | MASTER_EN); |
| 389 | } |
| 390 | |
| 391 | static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) |
| 392 | { |
| 393 | uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus); |
| 394 | return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) || |
| 395 | SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN); |
| 396 | } |
| 397 | |
| 398 | I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); |
| 399 | |
| 400 | #endif /* ASPEED_I2C_H */ |