| 1 | /* |
| 2 | * DesignWare I2C Module. |
| 3 | * |
| 4 | * Copyright 2021 Google LLC |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | #ifndef DESIGNWARE_I2C_H |
| 9 | #define DESIGNWARE_I2C_H |
| 10 | |
| 11 | #include "qemu/fifo8.h" |
| 12 | #include "hw/i2c/i2c.h" |
| 13 | #include "hw/core/irq.h" |
| 14 | #include "hw/core/register.h" |
| 15 | #include "hw/core/sysbus.h" |
| 16 | #include "qom/object.h" |
| 17 | |
| 18 | #define DESIGNWARE_I2C_R_MAX (0x100 / 4) |
| 19 | |
| 20 | #define DESIGNWARE_I2C_RX_FIFO_SIZE 16 |
| 21 | #define DESIGNWARE_I2C_TX_FIFO_SIZE 16 |
| 22 | |
| 23 | typedef enum DesignWareI2CStatus { |
| 24 | DW_I2C_STATUS_IDLE, |
| 25 | DW_I2C_STATUS_SENDING_ADDRESS, |
| 26 | DW_I2C_STATUS_SENDING, |
| 27 | DW_I2C_STATUS_RECEIVING, |
| 28 | } DesignWareI2CStatus; |
| 29 | |
| 30 | #define TYPE_DESIGNWARE_I2C "designware-i2c" |
| 31 | OBJECT_DECLARE_SIMPLE_TYPE(DesignWareI2CState, DESIGNWARE_I2C) |
| 32 | |
| 33 | /* |
| 34 | * struct DesignWareI2CState - DesignWare I2C device state. |
| 35 | * @bus: The underlying I2C Bus |
| 36 | * @irq: Interrupt line fired on transaction events. |
| 37 | * @rx_fifo: The FIFO buffer for receiving in FIFO mode. |
| 38 | */ |
| 39 | struct DesignWareI2CState { |
| 40 | SysBusDevice parent_obj; |
| 41 | |
| 42 | MemoryRegion iomem; |
| 43 | |
| 44 | I2CBus *bus; |
| 45 | qemu_irq irq; |
| 46 | |
| 47 | uint32_t regs[DESIGNWARE_I2C_R_MAX]; |
| 48 | RegisterInfo regs_info[DESIGNWARE_I2C_R_MAX]; |
| 49 | |
| 50 | /* fifo8_num_used(rx_fifo) should always equal DW_IC_RXFLR */ |
| 51 | Fifo8 rx_fifo; |
| 52 | |
| 53 | DesignWareI2CStatus status; |
| 54 | }; |
| 55 | |
| 56 | #endif /* DESIGNWARE_I2C_H */ |