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1 /*
2 * APIC support - internal interfaces
3 *
4 * Copyright (c) 2004-2005 Fabrice Bellard
5 * Copyright (c) 2011 Jan Kiszka, Siemens AG
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>
19 */
20
21 #ifndef QEMU_APIC_INTERNAL_H
22 #define QEMU_APIC_INTERNAL_H
23
24 #include "target/i386/cpu.h"
25 #include "hw/i386/apic.h"
26 #include "system/memory.h"
27 #include "qemu/timer.h"
28 #include "target/i386/cpu-qom.h"
29 #include "qom/object.h"
30
31 /* APIC Local Vector Table */
32 #define APIC_LVT_TIMER 0
33 #define APIC_LVT_THERMAL 1
34 #define APIC_LVT_PERFORM 2
35 #define APIC_LVT_LINT0 3
36 #define APIC_LVT_LINT1 4
37 #define APIC_LVT_ERROR 5
38 #define APIC_LVT_NB 6
39
40 /* APIC delivery modes */
41 #define APIC_DM_FIXED 0
42 #define APIC_DM_LOWPRI 1
43 #define APIC_DM_SMI 2
44 #define APIC_DM_NMI 4
45 #define APIC_DM_INIT 5
46 #define APIC_DM_SIPI 6
47 #define APIC_DM_EXTINT 7
48
49 /* APIC destination mode */
50 #define APIC_DESTMODE_PHYSICAL 0
51 #define APIC_DESTMODE_LOGICAL 1
52 #define APIC_DESTMODE_LOGICAL_FLAT 0xf
53 #define APIC_DESTMODE_LOGICAL_CLUSTER 0
54
55 #define APIC_TRIGGER_EDGE 0
56 #define APIC_TRIGGER_LEVEL 1
57
58 #define APIC_VECTOR_MASK 0xff
59 #define APIC_DCR_MASK 0xf
60
61 #define APIC_LVT_TIMER_SHIFT 17
62 #define APIC_LVT_MASKED_SHIFT 16
63 #define APIC_LVT_LEVEL_TRIGGER_SHIFT 15
64 #define APIC_LVT_REMOTE_IRR_SHIFT 14
65 #define APIC_LVT_INT_POLARITY_SHIFT 13
66 #define APIC_LVT_DELIV_STS_SHIFT 12
67 #define APIC_LVT_DELIV_MOD_SHIFT 8
68
69 #define APIC_LVT_TIMER_TSCDEADLINE (2 << APIC_LVT_TIMER_SHIFT)
70 #define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
71 #define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
72 #define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
73 #define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
74 #define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
75 #define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
76 #define APIC_LVT_DELIV_MOD (7 << APIC_LVT_DELIV_MOD_SHIFT)
77
78 #define APIC_ESR_ILL_ADDRESS_SHIFT 7
79 #define APIC_ESR_RECV_ILL_VECT_SHIFT 6
80 #define APIC_ESR_SEND_ILL_VECT_SHIFT 5
81 #define APIC_ESR_RECV_ACCEPT_SHIFT 3
82 #define APIC_ESR_SEND_ACCEPT_SHIFT 2
83 #define APIC_ESR_RECV_CHECK_SUM_SHIFT 1
84
85 #define APIC_ESR_ILLEGAL_ADDRESS (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
86 #define APIC_ESR_RECV_ILLEGAL_VECT (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
87 #define APIC_ESR_SEND_ILLEGAL_VECT (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
88 #define APIC_ESR_RECV_ACCEPT (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
89 #define APIC_ESR_SEND_ACCEPT (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
90 #define APIC_ESR_RECV_CHECK_SUM (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
91 #define APIC_ESR_SEND_CHECK_SUM 1
92
93 #define APIC_ICR_DEST_SHIFT 24
94 #define APIC_ICR_DEST_SHORT_SHIFT 18
95 #define APIC_ICR_TRIGGER_MOD_SHIFT 15
96 #define APIC_ICR_LEVEL_SHIFT 14
97 #define APIC_ICR_DELIV_STS_SHIFT 12
98 #define APIC_ICR_DEST_MOD_SHIFT 11
99 #define APIC_ICR_DELIV_MOD_SHIFT 8
100
101 #define APIC_ICR_DEST_SHORT (3 << APIC_ICR_DEST_SHORT_SHIFT)
102 #define APIC_ICR_TRIGGER_MOD (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
103 #define APIC_ICR_LEVEL (1 << APIC_ICR_LEVEL_SHIFT)
104 #define APIC_ICR_DELIV_STS (1 << APIC_ICR_DELIV_STS_SHIFT)
105 #define APIC_ICR_DEST_MOD (1 << APIC_ICR_DEST_MOD_SHIFT)
106 #define APIC_ICR_DELIV_MOD (7 << APIC_ICR_DELIV_MOD_SHIFT)
107
108 #define APIC_PR_CLASS_SHIFT 4
109 #define APIC_PR_SUB_CLASS 0xf
110
111 #define APIC_LOGDEST_XAPIC_SHIFT 4
112 #define APIC_LOGDEST_XAPIC_ID 0xf
113
114 #define APIC_LOGDEST_X2APIC_SHIFT 16
115 #define APIC_LOGDEST_X2APIC_ID 0xffff
116
117 #define APIC_SPURIO_FOCUS_SHIFT 9
118 #define APIC_SPURIO_ENABLED_SHIFT 8
119
120 #define APIC_SPURIO_FOCUS (1 << APIC_SPURIO_FOCUS_SHIFT)
121 #define APIC_SPURIO_ENABLED (1 << APIC_SPURIO_ENABLED_SHIFT)
122
123 #define APIC_SV_DIRECTED_IO (1 << 12)
124 #define APIC_SV_ENABLE (1 << 8)
125
126 #define VAPIC_ENABLE_BIT 0
127 #define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
128
129 #define TYPE_APIC_COMMON "apic-common"
130 typedef struct APICCommonClass APICCommonClass;
131 DECLARE_OBJ_CHECKERS(APICCommonState, APICCommonClass,
132 APIC_COMMON, TYPE_APIC_COMMON)
133
134 struct APICCommonClass {
135 DeviceClass parent_class;
136
137 DeviceRealize realize;
138 DeviceUnrealize unrealize;
139 int (*set_base)(APICCommonState *s, uint64_t val);
140 void (*set_tpr)(APICCommonState *s, uint8_t val);
141 uint8_t (*get_tpr)(APICCommonState *s);
142 void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
143 void (*vapic_base_update)(APICCommonState *s);
144 void (*external_nmi)(APICCommonState *s);
145 void (*pre_save)(APICCommonState *s);
146 void (*post_load)(APICCommonState *s);
147 void (*reset)(APICCommonState *s);
148 /* send_msi emulates an APIC bus and its proper place would be in a new
149 * device, but it's convenient to have it here for now.
150 */
151 void (*send_msi)(MSIMessage *msi);
152 };
153
154 struct APICCommonState {
155 /*< private >*/
156 DeviceState parent_obj;
157 /*< public >*/
158
159 MemoryRegion io_memory;
160 X86CPU *cpu;
161 uint32_t apicbase;
162 uint8_t id; /* legacy APIC ID */
163 uint32_t initial_apic_id;
164 uint8_t version;
165 uint8_t arb_id;
166 uint8_t tpr;
167 uint32_t spurious_vec;
168 uint8_t log_dest;
169 uint8_t dest_mode;
170 uint32_t isr[8]; /* in service register */
171 uint32_t tmr[8]; /* trigger mode register */
172 uint32_t irr[8]; /* interrupt request register */
173 uint32_t lvt[APIC_LVT_NB];
174 uint32_t esr; /* error register */
175 uint32_t icr[2];
176
177 uint32_t divide_conf;
178 int count_shift;
179 uint32_t initial_count;
180 int64_t initial_count_load_time;
181 int64_t next_time;
182 QEMUTimer *timer;
183 int64_t timer_expiry;
184 int sipi_vector;
185 int wait_for_sipi;
186
187 uint32_t vapic_control;
188 DeviceState *vapic;
189 hwaddr vapic_paddr; /* note: persistence via kvmvapic */
190 uint32_t extended_log_dest;
191 };
192
193 typedef struct VAPICState {
194 uint8_t tpr;
195 uint8_t isr;
196 uint8_t zero;
197 uint8_t irr;
198 uint8_t enabled;
199 } QEMU_PACKED VAPICState;
200
201 extern bool apic_report_tpr_access;
202
203 bool apic_next_timer(APICCommonState *s, int64_t current_time);
204 void apic_enable_tpr_access_reporting(APICCommonState *s, bool enable);
205 void apic_enable_vapic(APICCommonState *s, hwaddr paddr);
206
207 void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
208 TPRAccess access);
209
210 int apic_get_ppr(APICCommonState *s);
211 uint32_t apic_get_current_count(APICCommonState *s);
212
213 static inline void apic_set_bit(uint32_t *tab, int index)
214 {
215 int i, mask;
216 i = index >> 5;
217 mask = 1 << (index & 0x1f);
218 tab[i] |= mask;
219 }
220
221 static inline int apic_get_bit(uint32_t *tab, int index)
222 {
223 int i, mask;
224 i = index >> 5;
225 mask = 1 << (index & 0x1f);
226 return !!(tab[i] & mask);
227 }
228
229 APICCommonClass *apic_get_class(Error **errp);
230
231 #endif /* QEMU_APIC_INTERNAL_H */