| 1 | /* |
| 2 | * Copyright (c) 2019 Red Hat, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify it |
| 5 | * under the terms and conditions of the GNU General Public License, |
| 6 | * version 2 or later, as published by the Free Software Foundation. |
| 7 | * |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 11 | * more details. |
| 12 | * |
| 13 | * You should have received a copy of the GNU General Public License along with |
| 14 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 15 | */ |
| 16 | |
| 17 | #ifndef HW_I386_X86_H |
| 18 | #define HW_I386_X86_H |
| 19 | |
| 20 | #include "exec/hwaddr.h" |
| 21 | #include "system/memory.h" |
| 22 | |
| 23 | #include "hw/core/boards.h" |
| 24 | #include "hw/i386/topology.h" |
| 25 | #include "hw/intc/ioapic.h" |
| 26 | #include "hw/isa/isa.h" |
| 27 | #include "qom/object.h" |
| 28 | #include "system/igvm-cfg.h" |
| 29 | |
| 30 | struct X86MachineClass { |
| 31 | MachineClass parent; |
| 32 | |
| 33 | /* CPU and apic information: */ |
| 34 | bool apic_xrupt_override; |
| 35 | }; |
| 36 | |
| 37 | struct X86MachineState { |
| 38 | /*< private >*/ |
| 39 | MachineState parent; |
| 40 | |
| 41 | /*< public >*/ |
| 42 | |
| 43 | /* Pointers to devices and objects: */ |
| 44 | ISADevice *rtc; |
| 45 | FWCfgState *fw_cfg; |
| 46 | qemu_irq *gsi; |
| 47 | DeviceState *ioapic2; |
| 48 | GMappedFile *initrd_mapped_file; |
| 49 | HotplugHandler *acpi_dev; |
| 50 | |
| 51 | /* |
| 52 | * Map the whole BIOS just underneath the 4 GiB address boundary. Only used |
| 53 | * in the ROM (-bios) case. |
| 54 | */ |
| 55 | MemoryRegion bios; |
| 56 | |
| 57 | /* |
| 58 | * Map the upper 128 KiB of the BIOS just underneath the 1 MiB address |
| 59 | * boundary. |
| 60 | */ |
| 61 | MemoryRegion isa_bios; |
| 62 | |
| 63 | /* RAM information (sizes, addresses, configuration): */ |
| 64 | ram_addr_t below_4g_mem_size, above_4g_mem_size; |
| 65 | |
| 66 | /* Start address of the initial RAM above 4G */ |
| 67 | uint64_t above_4g_mem_start; |
| 68 | |
| 69 | /* CPU and apic information: */ |
| 70 | unsigned pci_irq_mask; |
| 71 | unsigned apic_id_limit; |
| 72 | uint16_t boot_cpus; |
| 73 | SgxEPCList *sgx_epc_list; |
| 74 | |
| 75 | OnOffAuto smm; |
| 76 | OnOffAuto acpi; |
| 77 | OnOffAuto pit; |
| 78 | OnOffAuto pic; |
| 79 | |
| 80 | char *oem_id; |
| 81 | char *oem_table_id; |
| 82 | /* |
| 83 | * Address space used by IOAPIC device. All IOAPIC interrupts |
| 84 | * will be translated to MSI messages in the address space. |
| 85 | */ |
| 86 | AddressSpace *ioapic_as; |
| 87 | |
| 88 | /* |
| 89 | * Ratelimit enforced on detected bus locks in guest. |
| 90 | * The default value of the bus_lock_ratelimit is 0 per second, |
| 91 | * which means no limitation on the guest's bus locks. |
| 92 | */ |
| 93 | uint64_t bus_lock_ratelimit; |
| 94 | |
| 95 | IgvmCfg *igvm; |
| 96 | }; |
| 97 | |
| 98 | #define X86_MACHINE_SMM "smm" |
| 99 | #define X86_MACHINE_ACPI "acpi" |
| 100 | #define X86_MACHINE_PIT "pit" |
| 101 | #define X86_MACHINE_PIC "pic" |
| 102 | #define X86_MACHINE_OEM_ID "x-oem-id" |
| 103 | #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id" |
| 104 | #define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit" |
| 105 | |
| 106 | #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") |
| 107 | OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) |
| 108 | |
| 109 | void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms); |
| 110 | uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, |
| 111 | unsigned int cpu_index); |
| 112 | |
| 113 | void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); |
| 114 | void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count); |
| 115 | void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, |
| 116 | DeviceState *dev, Error **errp); |
| 117 | void x86_cpu_plug(HotplugHandler *hotplug_dev, |
| 118 | DeviceState *dev, Error **errp); |
| 119 | void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, |
| 120 | DeviceState *dev, Error **errp); |
| 121 | void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, |
| 122 | DeviceState *dev, Error **errp); |
| 123 | |
| 124 | void x86_isa_bios_init(MemoryRegion *isa_bios, MemoryRegion *isa_memory, |
| 125 | MemoryRegion *bios, bool read_only); |
| 126 | void x86_bios_rom_init(X86MachineState *x86ms, const char *default_firmware, |
| 127 | MemoryRegion *rom_memory, bool isapc_ram_fw); |
| 128 | void x86_bios_rom_reload(X86MachineState *x86ms); |
| 129 | |
| 130 | void x86_load_linux(X86MachineState *x86ms, |
| 131 | FWCfgState *fw_cfg, |
| 132 | int acpi_data_size); |
| 133 | |
| 134 | bool x86_machine_is_smm_enabled(const X86MachineState *x86ms); |
| 135 | bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms); |
| 136 | |
| 137 | /* Global System Interrupts */ |
| 138 | |
| 139 | #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) |
| 140 | |
| 141 | typedef struct GSIState { |
| 142 | qemu_irq i8259_irq[ISA_NUM_IRQS]; |
| 143 | qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; |
| 144 | qemu_irq ioapic2_irq[IOAPIC_NUM_PINS]; |
| 145 | } GSIState; |
| 146 | |
| 147 | qemu_irq x86_allocate_cpu_irq(void); |
| 148 | void gsi_handler(void *opaque, int n, int level); |
| 149 | void ioapic_init_gsi(GSIState *gsi_state, Object *parent); |
| 150 | DeviceState *ioapic_init_secondary(GSIState *gsi_state); |
| 151 | |
| 152 | /* pc_sysfw.c */ |
| 153 | void x86_firmware_configure(hwaddr gpa, void *ptr, int size); |
| 154 | |
| 155 | #endif |