| 1 | /* |
| 2 | * ARM GIC support |
| 3 | * |
| 4 | * Copyright (c) 2012 Linaro Limited |
| 5 | * Copyright (c) 2015 Huawei. |
| 6 | * Copyright (c) 2015 Samsung Electronics Co., Ltd. |
| 7 | * Written by Peter Maydell |
| 8 | * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation, either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License along |
| 21 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 22 | */ |
| 23 | |
| 24 | #ifndef HW_ARM_GICV3_COMMON_H |
| 25 | #define HW_ARM_GICV3_COMMON_H |
| 26 | |
| 27 | #include "hw/core/sysbus.h" |
| 28 | #include "hw/intc/arm_gic_common.h" |
| 29 | #include "qom/object.h" |
| 30 | #include "qemu/notify.h" |
| 31 | |
| 32 | /* |
| 33 | * Maximum number of possible interrupts, determined by the GIC architecture. |
| 34 | * Note that this does not include LPIs. When implemented, these should be |
| 35 | * dealt with separately. |
| 36 | */ |
| 37 | #define GICV3_MAXIRQ 1020 |
| 38 | #define GICV3_MAXSPI (GICV3_MAXIRQ - GIC_INTERNAL) |
| 39 | |
| 40 | #define GICV3_LPI_INTID_START 8192 |
| 41 | |
| 42 | /* |
| 43 | * The redistributor in GICv3 has two 64KB frames per CPU; in |
| 44 | * GICv4 it has four 64KB frames per CPU. |
| 45 | */ |
| 46 | #define GICV3_REDIST_SIZE 0x20000 |
| 47 | #define GICV4_REDIST_SIZE 0x40000 |
| 48 | |
| 49 | /* Number of SGI target-list bits */ |
| 50 | #define GICV3_TARGETLIST_BITS 16 |
| 51 | |
| 52 | /* Maximum number of list registers (architectural limit) */ |
| 53 | #define GICV3_LR_MAX 16 |
| 54 | |
| 55 | /* |
| 56 | * For some distributor fields we want to model the array of 32-bit |
| 57 | * register values which hold various bitmaps corresponding to enabled, |
| 58 | * pending, etc bits. We use the set_bit32() etc family of functions |
| 59 | * from bitops.h for this. For a few cases we need to implement some |
| 60 | * extra operations. |
| 61 | * |
| 62 | * Each bitmap contains a bit for each interrupt. Although there is |
| 63 | * space for the PPIs and SGIs, those bits (the first 32) are never |
| 64 | * used as that state lives in the redistributor. The unused bits are |
| 65 | * provided purely so that interrupt X's state is always in bit X; this |
| 66 | * avoids bugs where we forget to subtract GIC_INTERNAL from an |
| 67 | * interrupt number. |
| 68 | */ |
| 69 | #define GIC_DECLARE_BITMAP(name) DECLARE_BITMAP32(name, GICV3_MAXIRQ) |
| 70 | #define GICV3_BMP_SIZE BITS_TO_U32S(GICV3_MAXIRQ) |
| 71 | |
| 72 | static inline void gic_bmp_replace_bit(int nr, uint32_t *addr, int val) |
| 73 | { |
| 74 | uint32_t mask = BIT32_MASK(nr); |
| 75 | uint32_t *p = addr + BIT32_WORD(nr); |
| 76 | |
| 77 | *p &= ~mask; |
| 78 | *p |= (val & 1U) << (nr % 32); |
| 79 | } |
| 80 | |
| 81 | /* Return a pointer to the 32-bit word containing the specified bit. */ |
| 82 | static inline uint32_t *gic_bmp_ptr32(uint32_t *addr, int nr) |
| 83 | { |
| 84 | return addr + BIT32_WORD(nr); |
| 85 | } |
| 86 | |
| 87 | typedef struct GICv3State GICv3State; |
| 88 | typedef struct GICv3CPUState GICv3CPUState; |
| 89 | |
| 90 | /* Some CPU interface registers come in three flavours: |
| 91 | * Group0, Group1 (Secure) and Group1 (NonSecure) |
| 92 | * (where the latter two are exposed as a single banked system register). |
| 93 | * In the state struct they are implemented as a 3-element array which |
| 94 | * can be indexed into by the GICV3_G0, GICV3_G1 and GICV3_G1NS constants. |
| 95 | * If the CPU doesn't support EL3 then the G1 element is unused. |
| 96 | * |
| 97 | * These constants are also used to communicate the group to use for |
| 98 | * an interrupt or SGI when it is passed between the cpu interface and |
| 99 | * the redistributor or distributor. For those purposes the receiving end |
| 100 | * must be prepared to cope with a Group 1 Secure interrupt even if it does |
| 101 | * not have security support enabled, because security can be disabled |
| 102 | * independently in the CPU and in the GIC. In that case the receiver should |
| 103 | * treat an incoming Group 1 Secure interrupt as if it were Group 0. |
| 104 | * (This architectural requirement is why the _G1 element is the unused one |
| 105 | * in a no-EL3 CPU: we would otherwise have to translate back and forth |
| 106 | * between (G0, G1NS) from the distributor and (G0, G1) in the CPU i/f.) |
| 107 | */ |
| 108 | #define GICV3_G0 0 |
| 109 | #define GICV3_G1 1 |
| 110 | #define GICV3_G1NS 2 |
| 111 | |
| 112 | /* ICC_CTLR_EL1, GICD_STATUSR and GICR_STATUSR are banked but not |
| 113 | * group-related, so those indices are just 0 for S and 1 for NS. |
| 114 | * (If the CPU or the GIC, respectively, don't support the Security |
| 115 | * extensions then the S element is unused.) |
| 116 | */ |
| 117 | #define GICV3_S 0 |
| 118 | #define GICV3_NS 1 |
| 119 | |
| 120 | typedef struct { |
| 121 | int irq; |
| 122 | uint8_t prio; |
| 123 | int grp; |
| 124 | bool nmi; |
| 125 | } PendingIrq; |
| 126 | |
| 127 | struct GICv3CPUState { |
| 128 | GICv3State *gic; |
| 129 | CPUState *cpu; |
| 130 | qemu_irq parent_irq; |
| 131 | qemu_irq parent_fiq; |
| 132 | qemu_irq parent_virq; |
| 133 | qemu_irq parent_vfiq; |
| 134 | qemu_irq parent_nmi; |
| 135 | qemu_irq parent_vnmi; |
| 136 | |
| 137 | /* Redistributor */ |
| 138 | uint32_t level; /* Current IRQ level */ |
| 139 | /* RD_base page registers */ |
| 140 | uint32_t gicr_ctlr; |
| 141 | uint64_t gicr_typer; |
| 142 | uint32_t gicr_statusr[2]; |
| 143 | uint32_t gicr_waker; |
| 144 | uint64_t gicr_propbaser; |
| 145 | uint64_t gicr_pendbaser; |
| 146 | /* SGI_base page registers */ |
| 147 | uint32_t gicr_igroupr0; |
| 148 | uint32_t gicr_ienabler0; |
| 149 | uint32_t gicr_ipendr0; |
| 150 | uint32_t gicr_iactiver0; |
| 151 | uint32_t gicr_inmir0; |
| 152 | uint32_t edge_trigger; /* ICFGR0 and ICFGR1 even bits */ |
| 153 | uint32_t gicr_igrpmodr0; |
| 154 | uint32_t gicr_nsacr; |
| 155 | uint8_t gicr_ipriorityr[GIC_INTERNAL]; |
| 156 | /* VLPI_base page registers */ |
| 157 | uint64_t gicr_vpropbaser; |
| 158 | uint64_t gicr_vpendbaser; |
| 159 | |
| 160 | /* CPU interface */ |
| 161 | uint64_t icc_sre_el1; |
| 162 | uint64_t icc_ctlr_el1[2]; |
| 163 | uint64_t icc_pmr_el1; |
| 164 | uint64_t icc_bpr[3]; |
| 165 | uint64_t icc_apr[3][4]; |
| 166 | uint64_t icc_igrpen[3]; |
| 167 | uint64_t icc_ctlr_el3; |
| 168 | |
| 169 | /* For KVM, cached copy of the kernel reset value of ICC_CTLR_EL1 */ |
| 170 | uint64_t kvm_reset_icc_ctlr_el1; |
| 171 | |
| 172 | /* Virtualization control interface */ |
| 173 | uint64_t ich_apr[3][4]; /* ich_apr[GICV3_G1][x] never used */ |
| 174 | uint64_t ich_hcr_el2; |
| 175 | uint64_t ich_lr_el2[GICV3_LR_MAX]; |
| 176 | uint64_t ich_vmcr_el2; |
| 177 | |
| 178 | /* Properties of the CPU interface. These are initialized from |
| 179 | * the settings in the CPU proper. |
| 180 | * If the number of implemented list registers is 0 then the |
| 181 | * virtualization support is not implemented. |
| 182 | */ |
| 183 | int num_list_regs; |
| 184 | int vpribits; /* number of virtual priority bits */ |
| 185 | int vprebits; /* number of virtual preemption bits */ |
| 186 | int pribits; /* number of physical priority bits */ |
| 187 | int prebits; /* number of physical preemption bits */ |
| 188 | |
| 189 | /* Current highest priority pending interrupt for this CPU. |
| 190 | * This is cached information that can be recalculated from the |
| 191 | * real state above; it doesn't need to be migrated. |
| 192 | */ |
| 193 | PendingIrq hppi; |
| 194 | |
| 195 | /* |
| 196 | * Cached information recalculated from LPI tables |
| 197 | * in guest memory |
| 198 | */ |
| 199 | PendingIrq hpplpi; |
| 200 | |
| 201 | /* Cached information recalculated from vLPI tables in guest memory */ |
| 202 | PendingIrq hppvlpi; |
| 203 | |
| 204 | /* This is temporary working state, to avoid a malloc in gicv3_update() */ |
| 205 | bool seenbetter; |
| 206 | |
| 207 | /* |
| 208 | * Whether the CPU interface has NMI support (FEAT_GICv3_NMI). The |
| 209 | * CPU interface may support NMIs even when the GIC proper (what the |
| 210 | * spec calls the IRI; the redistributors and distributor) does not. |
| 211 | */ |
| 212 | bool nmi_support; |
| 213 | }; |
| 214 | |
| 215 | /* |
| 216 | * The redistributor pages might be split into more than one region |
| 217 | * on some machine types if there are many CPUs. |
| 218 | */ |
| 219 | typedef struct GICv3RedistRegion { |
| 220 | GICv3State *gic; |
| 221 | MemoryRegion iomem; |
| 222 | uint32_t cpuidx; /* index of first CPU this region covers */ |
| 223 | } GICv3RedistRegion; |
| 224 | |
| 225 | struct GICv3State { |
| 226 | /*< private >*/ |
| 227 | SysBusDevice parent_obj; |
| 228 | /*< public >*/ |
| 229 | |
| 230 | MemoryRegion iomem_dist; /* Distributor */ |
| 231 | GICv3RedistRegion *redist_regions; /* Redistributor Regions */ |
| 232 | uint32_t *redist_region_count; /* redistributor count within each region */ |
| 233 | uint32_t nb_redist_regions; /* number of redist regions */ |
| 234 | |
| 235 | uint32_t first_cpu_idx; |
| 236 | uint32_t num_cpu; |
| 237 | uint32_t num_irq; |
| 238 | uint32_t revision; |
| 239 | uint32_t maint_irq; |
| 240 | bool lpi_enable; |
| 241 | bool nmi_support; |
| 242 | bool security_extn; |
| 243 | bool force_8bit_prio; |
| 244 | bool irq_reset_nonsecure; |
| 245 | bool gicd_no_migration_shift_bug; |
| 246 | |
| 247 | int dev_fd; /* kvm device fd if backed by kvm vgic support */ |
| 248 | Error *migration_blocker; |
| 249 | |
| 250 | MemoryRegion *dma; |
| 251 | AddressSpace dma_as; |
| 252 | |
| 253 | /* Distributor */ |
| 254 | |
| 255 | /* for a GIC with the security extensions the NS banked version of this |
| 256 | * register is just an alias of bit 1 of the S banked version. |
| 257 | */ |
| 258 | uint32_t gicd_ctlr; |
| 259 | uint32_t gicd_statusr[2]; |
| 260 | GIC_DECLARE_BITMAP(group); /* GICD_IGROUPR */ |
| 261 | GIC_DECLARE_BITMAP(grpmod); /* GICD_IGRPMODR */ |
| 262 | GIC_DECLARE_BITMAP(enabled); /* GICD_ISENABLER */ |
| 263 | GIC_DECLARE_BITMAP(pending); /* GICD_ISPENDR */ |
| 264 | GIC_DECLARE_BITMAP(active); /* GICD_ISACTIVER */ |
| 265 | GIC_DECLARE_BITMAP(level); /* Current level */ |
| 266 | GIC_DECLARE_BITMAP(edge_trigger); /* GICD_ICFGR even bits */ |
| 267 | GIC_DECLARE_BITMAP(nmi); /* GICD_INMIR */ |
| 268 | uint8_t gicd_ipriority[GICV3_MAXIRQ]; |
| 269 | uint64_t gicd_irouter[GICV3_MAXIRQ]; |
| 270 | /* Cached information: pointer to the cpu i/f for the CPUs specified |
| 271 | * in the IROUTER registers |
| 272 | */ |
| 273 | GICv3CPUState *gicd_irouter_target[GICV3_MAXIRQ]; |
| 274 | uint32_t gicd_nsacr[DIV_ROUND_UP(GICV3_MAXIRQ, 16)]; |
| 275 | |
| 276 | GICv3CPUState *cpu; |
| 277 | /* List of all ITSes connected to this GIC */ |
| 278 | GPtrArray *itslist; |
| 279 | |
| 280 | NotifierWithReturn cpr_notifier; |
| 281 | }; |
| 282 | |
| 283 | #define GICV3_BITMAP_ACCESSORS(BMP) \ |
| 284 | static inline void gicv3_gicd_##BMP##_set(GICv3State *s, int irq) \ |
| 285 | { \ |
| 286 | set_bit32(irq, s->BMP); \ |
| 287 | } \ |
| 288 | static inline int gicv3_gicd_##BMP##_test(GICv3State *s, int irq) \ |
| 289 | { \ |
| 290 | return test_bit32(irq, s->BMP); \ |
| 291 | } \ |
| 292 | static inline void gicv3_gicd_##BMP##_clear(GICv3State *s, int irq) \ |
| 293 | { \ |
| 294 | clear_bit32(irq, s->BMP); \ |
| 295 | } \ |
| 296 | static inline void gicv3_gicd_##BMP##_replace(GICv3State *s, \ |
| 297 | int irq, int value) \ |
| 298 | { \ |
| 299 | gic_bmp_replace_bit(irq, s->BMP, value); \ |
| 300 | } |
| 301 | |
| 302 | GICV3_BITMAP_ACCESSORS(group) |
| 303 | GICV3_BITMAP_ACCESSORS(grpmod) |
| 304 | GICV3_BITMAP_ACCESSORS(enabled) |
| 305 | GICV3_BITMAP_ACCESSORS(pending) |
| 306 | GICV3_BITMAP_ACCESSORS(active) |
| 307 | GICV3_BITMAP_ACCESSORS(level) |
| 308 | GICV3_BITMAP_ACCESSORS(edge_trigger) |
| 309 | GICV3_BITMAP_ACCESSORS(nmi) |
| 310 | |
| 311 | #define TYPE_ARM_GICV3_COMMON "arm-gicv3-common" |
| 312 | typedef struct ARMGICv3CommonClass ARMGICv3CommonClass; |
| 313 | DECLARE_OBJ_CHECKERS(GICv3State, ARMGICv3CommonClass, |
| 314 | ARM_GICV3_COMMON, TYPE_ARM_GICV3_COMMON) |
| 315 | |
| 316 | /* Types for GICv3 kernel-irqchip */ |
| 317 | #define TYPE_WHPX_GICV3 "whpx-arm-gicv3" |
| 318 | #define TYPE_HVF_GICV3 "hvf-arm-gicv3" |
| 319 | |
| 320 | struct ARMGICv3CommonClass { |
| 321 | /*< private >*/ |
| 322 | SysBusDeviceClass parent_class; |
| 323 | /*< public >*/ |
| 324 | |
| 325 | void (*pre_save)(GICv3State *s); |
| 326 | void (*post_load)(GICv3State *s); |
| 327 | }; |
| 328 | |
| 329 | void gicv3_init_irqs_and_mmio(GICv3State *s, qemu_irq_handler handler, |
| 330 | const MemoryRegionOps *ops); |
| 331 | |
| 332 | /** |
| 333 | * gicv3_class_name |
| 334 | * |
| 335 | * Return name of GICv3 class to use depending on whether KVM acceleration is |
| 336 | * in use. May throw an error if the chosen implementation is not available. |
| 337 | * |
| 338 | * Returns: class name to use |
| 339 | */ |
| 340 | const char *gicv3_class_name(void); |
| 341 | |
| 342 | /* HVF vGIC-specific state: stubbed out on a build with HVF disabled */ |
| 343 | extern const VMStateDescription vmstate_gicv3_hvf; |
| 344 | |
| 345 | #endif |