| 1 | /* |
| 2 | * ARM GICv5 emulation: Interrupt Routing Service (IRS) |
| 3 | * |
| 4 | * Copyright (c) 2025 Linaro Limited |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | */ |
| 8 | |
| 9 | #ifndef HW_INTC_ARM_GICV5_H |
| 10 | #define HW_INTC_ARM_GICV5_H |
| 11 | |
| 12 | #include "qom/object.h" |
| 13 | #include "hw/core/sysbus.h" |
| 14 | #include "hw/intc/arm_gicv5_common.h" |
| 15 | |
| 16 | #define TYPE_ARM_GICV5 "arm-gicv5" |
| 17 | |
| 18 | OBJECT_DECLARE_TYPE(GICv5, GICv5Class, ARM_GICV5) |
| 19 | |
| 20 | typedef struct GICv5ISTConfig { |
| 21 | hwaddr base; /* Base address */ |
| 22 | MemTxAttrs txattrs; /* TX attrs to use for this table */ |
| 23 | uint8_t id_bits; /* number of bits in an ID for this table */ |
| 24 | uint8_t l2_idx_bits; /* number of ID bits that index into L2 table */ |
| 25 | uint8_t istsz; /* L2 ISTE size in bytes */ |
| 26 | bool structure; /* true if using 2-level table */ |
| 27 | bool valid; /* true if this table is valid and usable */ |
| 28 | /* This caches IST information about pending LPIs */ |
| 29 | GHashTable *lpi_cache; |
| 30 | } GICv5ISTConfig; |
| 31 | |
| 32 | /* |
| 33 | * This class is for TCG-specific state for the GICv5. |
| 34 | */ |
| 35 | struct GICv5 { |
| 36 | GICv5Common parent_obj; |
| 37 | |
| 38 | /* This is the info from IRS_IST_BASER and IRS_IST_CFGR */ |
| 39 | GICv5ISTConfig phys_lpi_config[NUM_GICV5_DOMAINS]; |
| 40 | |
| 41 | /* We cache the HPPI for each CPU for each domain here */ |
| 42 | GICv5PendingIrq *hppi[NUM_GICV5_DOMAINS]; |
| 43 | }; |
| 44 | |
| 45 | struct GICv5Class { |
| 46 | GICv5CommonClass parent_class; |
| 47 | DeviceRealize parent_realize; |
| 48 | ResettablePhases parent_phases; |
| 49 | }; |
| 50 | |
| 51 | #endif |