| 1 | /* |
| 2 | * ASPEED Interrupt Controller (New) |
| 3 | * |
| 4 | * Andrew Jeffery <andrew@aj.id.au> |
| 5 | * |
| 6 | * Copyright 2016 IBM Corp. |
| 7 | * |
| 8 | * This code is licensed under the GPL version 2 or later. See |
| 9 | * the COPYING file in the top-level directory. |
| 10 | * |
| 11 | * Need to add SVIC and CVIC support |
| 12 | */ |
| 13 | #ifndef ASPEED_VIC_H |
| 14 | #define ASPEED_VIC_H |
| 15 | |
| 16 | #include "hw/core/sysbus.h" |
| 17 | #include "qom/object.h" |
| 18 | |
| 19 | #define TYPE_ASPEED_VIC "aspeed.vic" |
| 20 | OBJECT_DECLARE_SIMPLE_TYPE(AspeedVICState, ASPEED_VIC) |
| 21 | |
| 22 | #define ASPEED_VIC_NR_IRQS 51 |
| 23 | |
| 24 | struct AspeedVICState { |
| 25 | /*< private >*/ |
| 26 | SysBusDevice parent_obj; |
| 27 | |
| 28 | /*< public >*/ |
| 29 | MemoryRegion iomem; |
| 30 | qemu_irq irq; |
| 31 | qemu_irq fiq; |
| 32 | |
| 33 | uint64_t level; |
| 34 | uint64_t raw; |
| 35 | uint64_t select; |
| 36 | uint64_t enable; |
| 37 | uint64_t trigger; |
| 38 | |
| 39 | /* 0=edge, 1=level */ |
| 40 | uint64_t sense; |
| 41 | |
| 42 | /* 0=single-edge, 1=dual-edge */ |
| 43 | uint64_t dual_edge; |
| 44 | |
| 45 | /* 0=low-sensitive/falling-edge, 1=high-sensitive/rising-edge */ |
| 46 | uint64_t event; |
| 47 | }; |
| 48 | |
| 49 | #endif /* ASPEED_VIC_H */ |