| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * LoongArch direct interrupt controller definitions |
| 4 | * |
| 5 | * Copyright (C) 2025 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | |
| 8 | #include "qom/object.h" |
| 9 | #include "hw/core/sysbus.h" |
| 10 | #include "hw/loongarch/virt.h" |
| 11 | #include "system/memory.h" |
| 12 | #include "hw/pci-host/ls7a.h" |
| 13 | |
| 14 | #define NR_VECTORS 256 |
| 15 | #define IRQ_BIT_BASE 5 |
| 16 | #define IRQ_BIT_LEN 8 |
| 17 | #define CPU_BIT_BASE 13 |
| 18 | #define CPU_BIT_LEN 8 |
| 19 | |
| 20 | #define TYPE_LOONGARCH_DINTC "loongarch_dintc" |
| 21 | OBJECT_DECLARE_TYPE(LoongArchDINTCState, LoongArchDINTCClass, LOONGARCH_DINTC) |
| 22 | |
| 23 | typedef struct DINTCCore { |
| 24 | CPUState *cpu; |
| 25 | qemu_irq parent_irq; |
| 26 | uint64_t arch_id; |
| 27 | } DINTCCore; |
| 28 | |
| 29 | struct LoongArchDINTCState { |
| 30 | SysBusDevice parent_obj; |
| 31 | MemoryRegion dintc_mmio; |
| 32 | DINTCCore *cpu; |
| 33 | int dev_fd; |
| 34 | uint32_t num_cpu; |
| 35 | uint64_t msg_addr_base; |
| 36 | uint64_t msg_addr_size; |
| 37 | }; |
| 38 | |
| 39 | struct LoongArchDINTCClass { |
| 40 | SysBusDeviceClass parent_class; |
| 41 | |
| 42 | DeviceRealize parent_realize; |
| 43 | DeviceUnrealize parent_unrealize; |
| 44 | }; |
| 45 | |
| 46 | void kvm_dintc_realize(DeviceState *dev, Error **errp); |