| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * LoongArch 7A1000 I/O interrupt controller definitions |
| 4 | * |
| 5 | * Copyright (C) 2021 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | |
| 8 | #include "hw/core/sysbus.h" |
| 9 | #include "system/memory.h" |
| 10 | |
| 11 | #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" |
| 12 | OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) |
| 13 | |
| 14 | /* MSI irq start from 32 to 255 */ |
| 15 | #define PCH_MSI_IRQ_START 32 |
| 16 | #define PCH_MSI_IRQ_END 255 |
| 17 | #define PCH_MSI_IRQ_NUM 224 |
| 18 | |
| 19 | struct LoongArchPCHMSI { |
| 20 | SysBusDevice parent_obj; |
| 21 | qemu_irq *pch_msi_irq; |
| 22 | MemoryRegion msi_mmio; |
| 23 | /* irq base passed to upper extioi intc */ |
| 24 | unsigned int irq_base; |
| 25 | unsigned int irq_num; |
| 26 | }; |