@samitouri / QOSamiQemu
Code Commits Issues Pulls Sessions CI/CD
master
master
h 82 lines 2.67 KB
Raw
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * LoongArch 7A1000 I/O interrupt controller definitions
4 * Copyright (c) 2024 Loongson Technology Corporation Limited
5 */
6
7 #ifndef HW_LOONGARCH_PIC_COMMON_H
8 #define HW_LOONGARCH_PIC_COMMON_H
9
10 #include "hw/loongarch/virt.h"
11 #include "hw/core/sysbus.h"
12 #include "system/memory.h"
13
14 #define PCH_PIC_INT_ID 0x00
15 #define PCH_PIC_INT_ID_VAL 0x7
16 #define PCH_PIC_INT_ID_VER 0x1
17 #define PCH_PIC_INT_MASK 0x20
18 #define PCH_PIC_HTMSI_EN 0x40
19 #define PCH_PIC_INT_EDGE 0x60
20 #define PCH_PIC_INT_CLEAR 0x80
21 #define PCH_PIC_AUTO_CTRL0 0xc0
22 #define PCH_PIC_AUTO_CTRL1 0xe0
23 #define PCH_PIC_ROUTE_ENTRY 0x100
24 #define PCH_PIC_ROUTE_ENTRY_END 0x13f
25 #define PCH_PIC_HTMSI_VEC 0x200
26 #define PCH_PIC_HTMSI_VEC_END 0x23f
27 #define PCH_PIC_INT_REQUEST 0x380
28 #define PCH_PIC_INT_STATUS 0x3a0
29 #define PCH_PIC_INT_POL 0x3e0
30
31 #define TYPE_LOONGARCH_PIC_COMMON "loongarch_pic_common"
32 OBJECT_DECLARE_TYPE(LoongArchPICCommonState,
33 LoongArchPICCommonClass, LOONGARCH_PIC_COMMON)
34
35 union LoongArchPIC_ID {
36 struct {
37 uint8_t _reserved_0[3];
38 uint8_t id;
39 uint8_t version;
40 uint8_t _reserved_1;
41 uint8_t irq_num;
42 uint8_t _reserved_2;
43 } QEMU_PACKED desc;
44 uint64_t data;
45 };
46
47 struct LoongArchPICCommonState {
48 SysBusDevice parent_obj;
49
50 qemu_irq parent_irq[64];
51 union LoongArchPIC_ID id; /* 0x00 interrupt ID register */
52 uint64_t int_mask; /* 0x020 interrupt mask register */
53 uint64_t htmsi_en; /* 0x040 1=msi */
54 uint64_t intedge; /* 0x060 edge=1 level=0 */
55 uint64_t intclr; /* 0x080 clean edge int, set 1 clean, 0 noused */
56 uint64_t auto_crtl0; /* 0x0c0 */
57 uint64_t auto_crtl1; /* 0x0e0 */
58 uint64_t last_intirr; /* edge detection */
59 uint64_t intirr; /* 0x380 interrupt request register */
60 uint64_t intisr; /* 0x3a0 interrupt service register */
61 /*
62 * 0x3e0 interrupt level polarity selection
63 * register 0 for high level trigger
64 */
65 uint64_t int_polarity;
66
67 uint8_t route_entry[64]; /* 0x100 - 0x138 */
68 uint8_t htmsi_vector[64]; /* 0x200 - 0x238 */
69
70 MemoryRegion iomem;
71 unsigned int irq_num;
72 };
73
74 struct LoongArchPICCommonClass {
75 SysBusDeviceClass parent_class;
76
77 DeviceRealize parent_realize;
78 ResettablePhases parent_phases;
79 int (*pre_save)(LoongArchPICCommonState *s);
80 int (*post_load)(LoongArchPICCommonState *s, int version_id);
81 };
82 #endif /* HW_LOONGARCH_PIC_COMMON_H */