| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | /* |
| 3 | * Loongson ipi interrupt header files |
| 4 | * |
| 5 | * Copyright (C) 2021 Loongson Technology Corporation Limited |
| 6 | */ |
| 7 | |
| 8 | #ifndef HW_LOONGSON_IPI_COMMON_H |
| 9 | #define HW_LOONGSON_IPI_COMMON_H |
| 10 | |
| 11 | #include "qom/object.h" |
| 12 | #include "hw/core/sysbus.h" |
| 13 | #include "exec/memattrs.h" |
| 14 | #include "system/memory.h" |
| 15 | |
| 16 | #define IPI_MBX_NUM 4 |
| 17 | |
| 18 | #define TYPE_LOONGSON_IPI_COMMON "loongson_ipi_common" |
| 19 | OBJECT_DECLARE_TYPE(LoongsonIPICommonState, |
| 20 | LoongsonIPICommonClass, LOONGSON_IPI_COMMON) |
| 21 | |
| 22 | typedef struct IPICore { |
| 23 | LoongsonIPICommonState *ipi; |
| 24 | uint32_t status; |
| 25 | uint32_t en; |
| 26 | uint32_t set; |
| 27 | uint32_t clear; |
| 28 | /* 64bit buf divide into 2 32-bit buf */ |
| 29 | uint32_t buf[IPI_MBX_NUM * 2]; |
| 30 | qemu_irq irq; |
| 31 | uint64_t arch_id; |
| 32 | CPUState *cpu; |
| 33 | } IPICore; |
| 34 | |
| 35 | struct LoongsonIPICommonState { |
| 36 | SysBusDevice parent_obj; |
| 37 | |
| 38 | MemoryRegion ipi_iocsr_mem; |
| 39 | MemoryRegion ipi64_iocsr_mem; |
| 40 | uint32_t num_cpu; |
| 41 | IPICore *cpu; |
| 42 | }; |
| 43 | |
| 44 | struct LoongsonIPICommonClass { |
| 45 | SysBusDeviceClass parent_class; |
| 46 | |
| 47 | DeviceRealize parent_realize; |
| 48 | DeviceUnrealize parent_unrealize; |
| 49 | AddressSpace *(*get_iocsr_as)(CPUState *cpu); |
| 50 | int (*cpu_by_arch_id)(LoongsonIPICommonState *lics, int64_t id, |
| 51 | int *index, CPUState **pcs); |
| 52 | int (*pre_save)(void *opaque); |
| 53 | int (*post_load)(void *opaque, int version_id); |
| 54 | }; |
| 55 | |
| 56 | MemTxResult loongson_ipi_core_readl(void *opaque, hwaddr addr, uint64_t *data, |
| 57 | unsigned size, MemTxAttrs attrs); |
| 58 | MemTxResult loongson_ipi_core_writel(void *opaque, hwaddr addr, uint64_t val, |
| 59 | unsigned size, MemTxAttrs attrs); |
| 60 | |
| 61 | /* Mainy used by iocsr read and write */ |
| 62 | #define SMP_IPI_MAILBOX 0x1000ULL |
| 63 | |
| 64 | #define CORE_STATUS_OFF 0x0 |
| 65 | #define CORE_EN_OFF 0x4 |
| 66 | #define CORE_SET_OFF 0x8 |
| 67 | #define CORE_CLEAR_OFF 0xc |
| 68 | #define CORE_BUF_20 0x20 |
| 69 | #define CORE_BUF_28 0x28 |
| 70 | #define CORE_BUF_30 0x30 |
| 71 | #define CORE_BUF_38 0x38 |
| 72 | #define IOCSR_IPI_SEND 0x40 |
| 73 | #define IOCSR_MAIL_SEND 0x48 |
| 74 | #define IOCSR_ANY_SEND 0x158 |
| 75 | |
| 76 | #define MAIL_SEND_ADDR (SMP_IPI_MAILBOX + IOCSR_MAIL_SEND) |
| 77 | #define MAIL_SEND_OFFSET 0 |
| 78 | #define ANY_SEND_OFFSET (IOCSR_ANY_SEND - IOCSR_MAIL_SEND) |
| 79 | |
| 80 | #endif |