| 1 | /* |
| 2 | * RISC-V APLIC (Advanced Platform Level Interrupt Controller) interface |
| 3 | * |
| 4 | * Copyright (c) 2021 Western Digital Corporation or its affiliates. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, |
| 8 | * version 2 or later, as published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | |
| 19 | #ifndef HW_RISCV_APLIC_H |
| 20 | #define HW_RISCV_APLIC_H |
| 21 | |
| 22 | #include "hw/core/sysbus.h" |
| 23 | #include "qom/object.h" |
| 24 | |
| 25 | #define TYPE_RISCV_APLIC "riscv.aplic" |
| 26 | |
| 27 | typedef struct RISCVAPLICState RISCVAPLICState; |
| 28 | DECLARE_INSTANCE_CHECKER(RISCVAPLICState, RISCV_APLIC, TYPE_RISCV_APLIC) |
| 29 | |
| 30 | #define APLIC_MIN_SIZE 0x4000 |
| 31 | #define APLIC_SIZE_ALIGN(__x) (((__x) + (APLIC_MIN_SIZE - 1)) & \ |
| 32 | ~(APLIC_MIN_SIZE - 1)) |
| 33 | #define APLIC_SIZE(__num_harts) (APLIC_MIN_SIZE + \ |
| 34 | APLIC_SIZE_ALIGN(32 * (__num_harts))) |
| 35 | |
| 36 | struct RISCVAPLICState { |
| 37 | /*< private >*/ |
| 38 | SysBusDevice parent_obj; |
| 39 | qemu_irq *external_irqs; |
| 40 | |
| 41 | /*< public >*/ |
| 42 | MemoryRegion mmio; |
| 43 | uint32_t bitfield_words; |
| 44 | uint32_t domaincfg; |
| 45 | uint32_t mmsicfgaddr; |
| 46 | uint32_t mmsicfgaddrH; |
| 47 | uint32_t smsicfgaddr; |
| 48 | uint32_t smsicfgaddrH; |
| 49 | uint32_t genmsi; |
| 50 | uint32_t *sourcecfg; |
| 51 | uint32_t *state; |
| 52 | uint32_t *target; |
| 53 | uint32_t *idelivery; |
| 54 | uint32_t *iforce; |
| 55 | uint32_t *ithreshold; |
| 56 | |
| 57 | /* topology */ |
| 58 | #define QEMU_APLIC_MAX_CHILDREN 16 |
| 59 | struct RISCVAPLICState *parent; |
| 60 | struct RISCVAPLICState *children[QEMU_APLIC_MAX_CHILDREN]; |
| 61 | uint16_t num_children; |
| 62 | |
| 63 | /* config */ |
| 64 | uint32_t aperture_size; |
| 65 | uint32_t hartid_base; |
| 66 | uint32_t num_harts; |
| 67 | uint32_t iprio_mask; |
| 68 | uint32_t num_irqs; |
| 69 | bool msimode; |
| 70 | bool mmode; |
| 71 | |
| 72 | /* To support KVM aia=aplic-imsic with irqchip split mode */ |
| 73 | bool kvm_splitmode; |
| 74 | uint32_t kvm_msicfgaddr; |
| 75 | uint32_t kvm_msicfgaddrH; |
| 76 | }; |
| 77 | |
| 78 | void riscv_aplic_add_child(DeviceState *parent, DeviceState *child); |
| 79 | bool riscv_is_kvm_aia_aplic_imsic(bool msimode); |
| 80 | bool riscv_use_emulated_aplic(bool msimode); |
| 81 | void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr); |
| 82 | |
| 83 | DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, |
| 84 | uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, |
| 85 | uint32_t iprio_bits, bool msimode, bool mmode, DeviceState *parent); |
| 86 | |
| 87 | #endif |