| 1 | /* |
| 2 | * SiFive PLIC (Platform Level Interrupt Controller) interface |
| 3 | * |
| 4 | * Copyright (c) 2017 SiFive, Inc. |
| 5 | * |
| 6 | * This provides a RISC-V PLIC device |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms and conditions of the GNU General Public License, |
| 10 | * version 2 or later, as published by the Free Software Foundation. |
| 11 | * |
| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 19 | */ |
| 20 | |
| 21 | #ifndef HW_SIFIVE_PLIC_H |
| 22 | #define HW_SIFIVE_PLIC_H |
| 23 | |
| 24 | #include "hw/core/sysbus.h" |
| 25 | #include "qom/object.h" |
| 26 | |
| 27 | #define TYPE_SIFIVE_PLIC "riscv.sifive.plic" |
| 28 | |
| 29 | typedef struct SiFivePLICState SiFivePLICState; |
| 30 | DECLARE_INSTANCE_CHECKER(SiFivePLICState, SIFIVE_PLIC, |
| 31 | TYPE_SIFIVE_PLIC) |
| 32 | |
| 33 | typedef enum PLICMode { |
| 34 | PLICMode_U, |
| 35 | PLICMode_S, |
| 36 | PLICMode_M |
| 37 | } PLICMode; |
| 38 | |
| 39 | typedef struct PLICAddr { |
| 40 | uint32_t addrid; |
| 41 | uint32_t hartid; |
| 42 | PLICMode mode; |
| 43 | } PLICAddr; |
| 44 | |
| 45 | struct SiFivePLICState { |
| 46 | /*< private >*/ |
| 47 | SysBusDevice parent_obj; |
| 48 | |
| 49 | /*< public >*/ |
| 50 | MemoryRegion mmio; |
| 51 | uint32_t num_addrs; |
| 52 | uint32_t num_harts; |
| 53 | uint32_t bitfield_words; |
| 54 | uint32_t num_enables; |
| 55 | PLICAddr *addr_config; |
| 56 | uint32_t *source_priority; |
| 57 | uint32_t *target_priority; |
| 58 | uint32_t *pending; |
| 59 | uint32_t *claimed; |
| 60 | uint32_t *enable; |
| 61 | |
| 62 | /* config */ |
| 63 | char *hart_config; |
| 64 | uint32_t hartid_base; |
| 65 | uint32_t num_sources; |
| 66 | uint32_t num_priorities; |
| 67 | uint32_t priority_base; |
| 68 | uint32_t pending_base; |
| 69 | uint32_t enable_base; |
| 70 | uint32_t enable_stride; |
| 71 | uint32_t context_base; |
| 72 | uint32_t context_stride; |
| 73 | uint32_t aperture_size; |
| 74 | |
| 75 | qemu_irq *m_external_irqs; |
| 76 | qemu_irq *s_external_irqs; |
| 77 | }; |
| 78 | |
| 79 | DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, |
| 80 | uint32_t num_harts, |
| 81 | uint32_t hartid_base, uint32_t num_sources, |
| 82 | uint32_t num_priorities, uint32_t priority_base, |
| 83 | uint32_t pending_base, uint32_t enable_base, |
| 84 | uint32_t enable_stride, uint32_t context_base, |
| 85 | uint32_t context_stride, uint32_t aperture_size); |
| 86 | |
| 87 | #endif |