| 1 | /* |
| 2 | * ASPEED Hash and Crypto Engine |
| 3 | * |
| 4 | * Copyright (c) 2024 Seagate Technology LLC and/or its Affiliates |
| 5 | * Copyright (C) 2021 IBM Corp. |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 8 | */ |
| 9 | |
| 10 | #ifndef ASPEED_HACE_H |
| 11 | #define ASPEED_HACE_H |
| 12 | |
| 13 | #include "hw/core/sysbus.h" |
| 14 | #include "crypto/hash.h" |
| 15 | |
| 16 | #define TYPE_ASPEED_HACE "aspeed.hace" |
| 17 | #define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" |
| 18 | #define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500" |
| 19 | #define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600" |
| 20 | #define TYPE_ASPEED_AST1030_HACE TYPE_ASPEED_HACE "-ast1030" |
| 21 | #define TYPE_ASPEED_AST2700_HACE TYPE_ASPEED_HACE "-ast2700" |
| 22 | |
| 23 | OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) |
| 24 | |
| 25 | #define ASPEED_HACE_MAX_SG 256 /* max number of entries */ |
| 26 | |
| 27 | struct AspeedHACEState { |
| 28 | SysBusDevice parent; |
| 29 | |
| 30 | MemoryRegion iomem; |
| 31 | qemu_irq irq; |
| 32 | |
| 33 | uint32_t *regs; |
| 34 | uint32_t total_req_len; |
| 35 | |
| 36 | MemoryRegion *dram_mr; |
| 37 | AddressSpace dram_as; |
| 38 | |
| 39 | QCryptoHash *hash_ctx; |
| 40 | }; |
| 41 | |
| 42 | |
| 43 | struct AspeedHACEClass { |
| 44 | SysBusDeviceClass parent_class; |
| 45 | |
| 46 | const MemoryRegionOps *reg_ops; |
| 47 | uint32_t src_mask; |
| 48 | uint32_t dest_mask; |
| 49 | uint32_t key_mask; |
| 50 | uint32_t hash_mask; |
| 51 | uint64_t nr_regs; |
| 52 | uint32_t src_hi_mask; |
| 53 | uint32_t dest_hi_mask; |
| 54 | uint32_t key_hi_mask; |
| 55 | bool has_dma64; |
| 56 | }; |
| 57 | |
| 58 | #endif /* ASPEED_HACE_H */ |