| 1 | /* |
| 2 | * ASPEED LPC Controller |
| 3 | * |
| 4 | * Copyright (C) 2017-2018 IBM Corp. |
| 5 | * |
| 6 | * This code is licensed under the GPL version 2 or later. See |
| 7 | * the COPYING file in the top-level directory. |
| 8 | */ |
| 9 | |
| 10 | #ifndef ASPEED_LPC_H |
| 11 | #define ASPEED_LPC_H |
| 12 | |
| 13 | #include "hw/core/sysbus.h" |
| 14 | |
| 15 | #define TYPE_ASPEED_LPC "aspeed.lpc" |
| 16 | #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC) |
| 17 | |
| 18 | #define ASPEED_LPC_NR_REGS (0x260 >> 2) |
| 19 | |
| 20 | enum aspeed_lpc_subdevice { |
| 21 | aspeed_lpc_kcs_1 = 0, |
| 22 | aspeed_lpc_kcs_2, |
| 23 | aspeed_lpc_kcs_3, |
| 24 | aspeed_lpc_kcs_4, |
| 25 | aspeed_lpc_ibt, |
| 26 | }; |
| 27 | |
| 28 | #define ASPEED_LPC_NR_SUBDEVS 5 |
| 29 | |
| 30 | typedef struct AspeedLPCState { |
| 31 | /* <private> */ |
| 32 | SysBusDevice parent; |
| 33 | |
| 34 | /*< public >*/ |
| 35 | MemoryRegion iomem; |
| 36 | qemu_irq irq; |
| 37 | |
| 38 | qemu_irq subdevice_irqs[ASPEED_LPC_NR_SUBDEVS]; |
| 39 | uint32_t subdevice_irqs_pending; |
| 40 | |
| 41 | uint32_t regs[ASPEED_LPC_NR_REGS]; |
| 42 | uint32_t hicr7; |
| 43 | } AspeedLPCState; |
| 44 | |
| 45 | #endif /* ASPEED_LPC_H */ |