| 1 | /* |
| 2 | * IMX31 Clock Control Module |
| 3 | * |
| 4 | * Copyright (C) 2012 NICTA |
| 5 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
| 6 | * |
| 7 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
| 8 | * See the COPYING file in the top-level directory. |
| 9 | */ |
| 10 | |
| 11 | #ifndef IMX31_CCM_H |
| 12 | #define IMX31_CCM_H |
| 13 | |
| 14 | #include "hw/misc/imx_ccm.h" |
| 15 | #include "qom/object.h" |
| 16 | |
| 17 | #define IMX31_CCM_CCMR_REG 0 |
| 18 | #define IMX31_CCM_PDR0_REG 1 |
| 19 | #define IMX31_CCM_PDR1_REG 2 |
| 20 | #define IMX31_CCM_RCSR_REG 3 |
| 21 | #define IMX31_CCM_MPCTL_REG 4 |
| 22 | #define IMX31_CCM_UPCTL_REG 5 |
| 23 | #define IMX31_CCM_SPCTL_REG 6 |
| 24 | #define IMX31_CCM_COSR_REG 7 |
| 25 | #define IMX31_CCM_CGR0_REG 8 |
| 26 | #define IMX31_CCM_CGR1_REG 9 |
| 27 | #define IMX31_CCM_CGR2_REG 10 |
| 28 | #define IMX31_CCM_WIMR_REG 11 |
| 29 | #define IMX31_CCM_LDC_REG 12 |
| 30 | #define IMX31_CCM_DCVR0_REG 13 |
| 31 | #define IMX31_CCM_DCVR1_REG 14 |
| 32 | #define IMX31_CCM_DCVR2_REG 15 |
| 33 | #define IMX31_CCM_DCVR3_REG 16 |
| 34 | #define IMX31_CCM_LTR0_REG 17 |
| 35 | #define IMX31_CCM_LTR1_REG 18 |
| 36 | #define IMX31_CCM_LTR2_REG 19 |
| 37 | #define IMX31_CCM_LTR3_REG 20 |
| 38 | #define IMX31_CCM_LTBR0_REG 21 |
| 39 | #define IMX31_CCM_LTBR1_REG 22 |
| 40 | #define IMX31_CCM_PMCR0_REG 23 |
| 41 | #define IMX31_CCM_PMCR1_REG 24 |
| 42 | #define IMX31_CCM_PDR2_REG 25 |
| 43 | #define IMX31_CCM_MAX_REG 26 |
| 44 | |
| 45 | /* CCMR */ |
| 46 | #define CCMR_FPME (1<<0) |
| 47 | #define CCMR_MPE (1<<3) |
| 48 | #define CCMR_MDS (1<<7) |
| 49 | #define CCMR_FPMF (1<<26) |
| 50 | #define CCMR_PRCS (3<<1) |
| 51 | |
| 52 | #define PMCR0_DFSUP1 (1<<31) |
| 53 | |
| 54 | /* PDR0 */ |
| 55 | #define PDR0_MCU_PODF_SHIFT (0) |
| 56 | #define PDR0_MCU_PODF_MASK (0x7) |
| 57 | #define PDR0_MAX_PODF_SHIFT (3) |
| 58 | #define PDR0_MAX_PODF_MASK (0x7) |
| 59 | #define PDR0_IPG_PODF_SHIFT (6) |
| 60 | #define PDR0_IPG_PODF_MASK (0x3) |
| 61 | #define PDR0_NFC_PODF_SHIFT (8) |
| 62 | #define PDR0_NFC_PODF_MASK (0x7) |
| 63 | #define PDR0_HSP_PODF_SHIFT (11) |
| 64 | #define PDR0_HSP_PODF_MASK (0x7) |
| 65 | #define PDR0_PER_PODF_SHIFT (16) |
| 66 | #define PDR0_PER_PODF_MASK (0x1f) |
| 67 | #define PDR0_CSI_PODF_SHIFT (23) |
| 68 | #define PDR0_CSI_PODF_MASK (0x1ff) |
| 69 | |
| 70 | #define EXTRACT(value, name) (((value) >> PDR0_##name##_PODF_SHIFT) \ |
| 71 | & PDR0_##name##_PODF_MASK) |
| 72 | #define INSERT(value, name) (((value) & PDR0_##name##_PODF_MASK) << \ |
| 73 | PDR0_##name##_PODF_SHIFT) |
| 74 | |
| 75 | #define TYPE_IMX31_CCM "imx31.ccm" |
| 76 | OBJECT_DECLARE_SIMPLE_TYPE(IMX31CCMState, IMX31_CCM) |
| 77 | |
| 78 | struct IMX31CCMState { |
| 79 | /* <private> */ |
| 80 | IMXCCMState parent_obj; |
| 81 | |
| 82 | /* <public> */ |
| 83 | MemoryRegion iomem; |
| 84 | |
| 85 | uint32_t reg[IMX31_CCM_MAX_REG]; |
| 86 | |
| 87 | }; |
| 88 | |
| 89 | #endif /* IMX31_CCM_H */ |