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1 /*
2 * A test device for IOMMU
3 *
4 * Copyright (c) 2026 Phytium Technology
5 *
6 * Author:
7 * Tao Tang <tangtao1634@phytium.com.cn>
8 *
9 * SPDX-License-Identifier: GPL-2.0-or-later
10 */
11
12 #ifndef HW_MISC_IOMMU_TESTDEV_H
13 #define HW_MISC_IOMMU_TESTDEV_H
14
15 #include "hw/pci/pci.h"
16
17 #define IOMMU_TESTDEV_VENDOR_ID PCI_VENDOR_ID_REDHAT
18 #define IOMMU_TESTDEV_DEVICE_ID PCI_DEVICE_ID_REDHAT_TEST
19
20 /* DMA_ATTRS register bit definitions which shadow some fields in MemTxAttrs */
21 #define ITD_ATTRS_SECURE_SHIFT 0
22 #define ITD_ATTRS_SECURE_MASK 0x1
23 #define ITD_ATTRS_SPACE_SHIFT 1
24 #define ITD_ATTRS_SPACE_MASK 0x3
25 #define ITD_ATTRS_SPACE_VALID_SHIFT 3
26 #define ITD_ATTRS_SPACE_VALID_MASK 0x1
27
28 #define ITD_ATTRS_SPACE_SECURE 0
29 #define ITD_ATTRS_SPACE_NONSECURE 1
30
31 /* Helper macros for setting fields */
32 #define ITD_ATTRS_SET_SECURE(attrs, val) \
33 (((attrs) & ~(ITD_ATTRS_SECURE_MASK << ITD_ATTRS_SECURE_SHIFT)) | \
34 (((val) & ITD_ATTRS_SECURE_MASK) << ITD_ATTRS_SECURE_SHIFT))
35
36 #define ITD_ATTRS_SET_SPACE(attrs, val) \
37 (((attrs) & ~(ITD_ATTRS_SPACE_MASK << ITD_ATTRS_SPACE_SHIFT)) | \
38 (((val) & ITD_ATTRS_SPACE_MASK) << ITD_ATTRS_SPACE_SHIFT))
39
40 #define ITD_ATTRS_SET_SPACE_VALID(attrs, val) \
41 (((attrs) & ~(ITD_ATTRS_SPACE_VALID_MASK << \
42 ITD_ATTRS_SPACE_VALID_SHIFT)) | \
43 (((val) & ITD_ATTRS_SPACE_VALID_MASK) << \
44 ITD_ATTRS_SPACE_VALID_SHIFT))
45
46 /* Helper macros for getting fields */
47 #define ITD_ATTRS_GET_SECURE(attrs) \
48 (((attrs) >> ITD_ATTRS_SECURE_SHIFT) & ITD_ATTRS_SECURE_MASK)
49
50 #define ITD_ATTRS_GET_SPACE(attrs) \
51 (((attrs) >> ITD_ATTRS_SPACE_SHIFT) & ITD_ATTRS_SPACE_MASK)
52
53 #define ITD_ATTRS_GET_SPACE_VALID(attrs) \
54 (((attrs) >> ITD_ATTRS_SPACE_VALID_SHIFT) & \
55 ITD_ATTRS_SPACE_VALID_MASK)
56
57 /* DMA result/status values shared with tests */
58 #define ITD_DMA_RESULT_IDLE 0xffffffffu
59 #define ITD_DMA_RESULT_BUSY 0xfffffffeu
60 #define ITD_DMA_ERR_BAD_LEN 0xdead0001u
61 #define ITD_DMA_ERR_TX_FAIL 0xdead0002u
62 #define ITD_DMA_ERR_RD_FAIL 0xdead0003u
63 #define ITD_DMA_ERR_MISMATCH 0xdead0004u
64 #define ITD_DMA_ERR_NOT_ARMED 0xdead0005u
65 #define ITD_DMA_ERR_BAD_ATTRS 0xdead0006u
66
67 #define ITD_DMA_WRITE_VAL 0x12345678u
68
69 /* DMA doorbell bits */
70 #define ITD_DMA_DBELL_ARM 0x1u
71
72 /* BAR0 layout of iommu-testdev */
73 enum {
74 ITD_REG_DMA_TRIGGERING = 0x00,
75 ITD_REG_DMA_GVA_LO = 0x04,
76 ITD_REG_DMA_GVA_HI = 0x08,
77 ITD_REG_DMA_LEN = 0x0c,
78 ITD_REG_DMA_RESULT = 0x10,
79 ITD_REG_DMA_DBELL = 0x14,
80 /* [0] secure,[2:1] ArmSecuritySpace,[3] space_valid */
81 ITD_REG_DMA_ATTRS = 0x18,
82 ITD_REG_DMA_GPA_LO = 0x1c,
83 ITD_REG_DMA_GPA_HI = 0x20,
84 BAR0_SIZE = 0x1000,
85 };
86
87 #endif /* HW_MISC_IOMMU_TESTDEV_H */