| 1 | /* |
| 2 | * ARM IoTKit system control element |
| 3 | * |
| 4 | * Copyright (c) 2018 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * This is a model of the "system control element" which is part of the |
| 14 | * Arm IoTKit and documented in |
| 15 | * https://developer.arm.com/documentation/ecm0601256/latest |
| 16 | * Specifically, it implements the "system information block" and |
| 17 | * "system control register" blocks. |
| 18 | * |
| 19 | * QEMU interface: |
| 20 | * + QOM property "sse-version": indicates which SSE version this is part of |
| 21 | * (used to identify whether to provide SSE-200-only registers, etc) |
| 22 | * + sysbus MMIO region 0: the system information register bank |
| 23 | * + sysbus MMIO region 1: the system control register bank |
| 24 | */ |
| 25 | |
| 26 | #ifndef HW_MISC_IOTKIT_SYSCTL_H |
| 27 | #define HW_MISC_IOTKIT_SYSCTL_H |
| 28 | |
| 29 | #include "hw/core/sysbus.h" |
| 30 | #include "qom/object.h" |
| 31 | |
| 32 | #define TYPE_IOTKIT_SYSCTL "iotkit-sysctl" |
| 33 | OBJECT_DECLARE_SIMPLE_TYPE(IoTKitSysCtl, IOTKIT_SYSCTL) |
| 34 | |
| 35 | struct IoTKitSysCtl { |
| 36 | /*< private >*/ |
| 37 | SysBusDevice parent_obj; |
| 38 | |
| 39 | /*< public >*/ |
| 40 | MemoryRegion iomem; |
| 41 | |
| 42 | uint32_t secure_debug; |
| 43 | uint32_t reset_syndrome; |
| 44 | uint32_t reset_mask; |
| 45 | uint32_t gretreg; |
| 46 | uint32_t initsvtor0; |
| 47 | uint32_t cpuwait; |
| 48 | uint32_t wicctrl; |
| 49 | uint32_t scsecctrl; |
| 50 | uint32_t fclk_div; |
| 51 | uint32_t sysclk_div; |
| 52 | uint32_t clock_force; |
| 53 | uint32_t initsvtor1; |
| 54 | uint32_t nmi_enable; |
| 55 | uint32_t ewctrl; |
| 56 | uint32_t pwrctrl; |
| 57 | uint32_t pdcm_pd_sys_sense; |
| 58 | uint32_t pdcm_pd_sram0_sense; |
| 59 | uint32_t pdcm_pd_sram1_sense; |
| 60 | uint32_t pdcm_pd_sram2_sense; |
| 61 | uint32_t pdcm_pd_sram3_sense; |
| 62 | uint32_t pdcm_pd_cpu0_sense; |
| 63 | uint32_t pdcm_pd_vmr0_sense; |
| 64 | uint32_t pdcm_pd_vmr1_sense; |
| 65 | |
| 66 | /* Properties */ |
| 67 | uint32_t sse_version; |
| 68 | uint32_t cpuwait_rst; |
| 69 | uint32_t initsvtor0_rst; |
| 70 | uint32_t initsvtor1_rst; |
| 71 | }; |
| 72 | |
| 73 | #endif |