| 1 | /* |
| 2 | * Kendryte K230 DDR controller and PHY models |
| 3 | * |
| 4 | * Device state and type declarations for the K230 DDRC CFG and K230 DDR PHY |
| 5 | * registers. |
| 6 | * |
| 7 | * Copyright (c) 2026 Junze Cao <caojunze424@gmail.com> |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 10 | */ |
| 11 | |
| 12 | #ifndef HW_MISC_K230_DDR_H |
| 13 | #define HW_MISC_K230_DDR_H |
| 14 | |
| 15 | #include "hw/core/sysbus.h" |
| 16 | |
| 17 | #define K230_DDRC_MMIO_SIZE 0x02000000 |
| 18 | #define K230_DDR_PHY_MMIO_SIZE 0x00400000 |
| 19 | |
| 20 | #define K230_DDRC_REG_SIZE 0x328 |
| 21 | #define K230_DDRC_REG_COUNT (K230_DDRC_REG_SIZE / sizeof(uint32_t)) |
| 22 | |
| 23 | #define K230_DDR_PHY_ANIB_COUNT 10 |
| 24 | #define K230_DDR_PHY_DBYTE_COUNT 4 |
| 25 | #define K230_DDR_PHY_NIBBLES_PER_DBYTE 2 |
| 26 | |
| 27 | #define TYPE_K230_DDR_CFG "riscv.k230.ddr-cfg" |
| 28 | OBJECT_DECLARE_SIMPLE_TYPE(K230DDRCfgState, K230_DDR_CFG) |
| 29 | |
| 30 | #define TYPE_K230_DDR_PHY "riscv.k230.ddr-phy" |
| 31 | OBJECT_DECLARE_SIMPLE_TYPE(K230DDRPhyState, K230_DDR_PHY) |
| 32 | |
| 33 | struct K230DDRCfgState { |
| 34 | SysBusDevice parent_obj; |
| 35 | |
| 36 | MemoryRegion mmio; |
| 37 | K230DDRPhyState *phy; |
| 38 | uint32_t regs[K230_DDRC_REG_COUNT]; |
| 39 | bool initialized; |
| 40 | }; |
| 41 | |
| 42 | struct K230DDRPhyState { |
| 43 | SysBusDevice parent_obj; |
| 44 | |
| 45 | MemoryRegion mmio; |
| 46 | uint16_t atx_impedance[K230_DDR_PHY_ANIB_COUNT]; |
| 47 | uint16_t tx_impedance_ctrl1[K230_DDR_PHY_DBYTE_COUNT] |
| 48 | [K230_DDR_PHY_NIBBLES_PER_DBYTE]; |
| 49 | uint16_t tx_odt_drv_stren[K230_DDR_PHY_DBYTE_COUNT] |
| 50 | [K230_DDR_PHY_NIBBLES_PER_DBYTE]; |
| 51 | uint16_t dfi_init_complete; |
| 52 | uint16_t vref_in_global; |
| 53 | uint16_t micro_cont_mux_sel; |
| 54 | bool training_trigger_seen; |
| 55 | bool training_complete; |
| 56 | bool mailbox_message_pending; |
| 57 | }; |
| 58 | |
| 59 | #endif |