| 1 | /* |
| 2 | * Microchip PolarFire SoC DDR Memory Controller module emulation |
| 3 | * |
| 4 | * Copyright (c) 2020 Wind River Systems, Inc. |
| 5 | * |
| 6 | * Author: |
| 7 | * Bin Meng <bin.meng@windriver.com> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 or |
| 12 | * (at your option) version 3 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License along |
| 20 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
| 21 | */ |
| 22 | |
| 23 | #ifndef MCHP_PFSOC_DMC_H |
| 24 | #define MCHP_PFSOC_DMC_H |
| 25 | |
| 26 | #include "hw/core/sysbus.h" |
| 27 | |
| 28 | /* DDR SGMII PHY module */ |
| 29 | |
| 30 | #define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000 |
| 31 | |
| 32 | typedef struct MchpPfSoCDdrSgmiiPhyState { |
| 33 | SysBusDevice parent; |
| 34 | MemoryRegion sgmii_phy; |
| 35 | } MchpPfSoCDdrSgmiiPhyState; |
| 36 | |
| 37 | #define TYPE_MCHP_PFSOC_DDR_SGMII_PHY "mchp.pfsoc.ddr_sgmii_phy" |
| 38 | |
| 39 | #define MCHP_PFSOC_DDR_SGMII_PHY(obj) \ |
| 40 | OBJECT_CHECK(MchpPfSoCDdrSgmiiPhyState, (obj), \ |
| 41 | TYPE_MCHP_PFSOC_DDR_SGMII_PHY) |
| 42 | |
| 43 | /* DDR CFG module */ |
| 44 | |
| 45 | #define MCHP_PFSOC_DDR_CFG_REG_SIZE 0x40000 |
| 46 | |
| 47 | typedef struct MchpPfSoCDdrCfgState { |
| 48 | SysBusDevice parent; |
| 49 | MemoryRegion cfg; |
| 50 | } MchpPfSoCDdrCfgState; |
| 51 | |
| 52 | #define TYPE_MCHP_PFSOC_DDR_CFG "mchp.pfsoc.ddr_cfg" |
| 53 | |
| 54 | #define MCHP_PFSOC_DDR_CFG(obj) \ |
| 55 | OBJECT_CHECK(MchpPfSoCDdrCfgState, (obj), \ |
| 56 | TYPE_MCHP_PFSOC_DDR_CFG) |
| 57 | |
| 58 | #endif /* MCHP_PFSOC_DMC_H */ |