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1 /*
2 * QEMU MOS6522 VIA emulation
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2018 Mark Cave-Ayland
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #ifndef MOS6522_H
28 #define MOS6522_H
29
30 #include "exec/hwaddr.h"
31 #include "hw/core/sysbus.h"
32 #include "qom/object.h"
33
34 #define MOS6522_NUM_REGS 16
35
36 /* Bits in ACR */
37 #define SR_CTRL 0x1c /* Shift register control bits */
38 #define SR_EXT 0x0c /* Shift on external clock */
39 #define SR_OUT 0x10 /* Shift out if 1 */
40
41 /* Bits in IFR and IER */
42 #define IER_SET 0x80 /* set bits in IER */
43 #define IER_CLR 0 /* clear bits in IER */
44
45 #define CA2_INT_BIT 0
46 #define CA1_INT_BIT 1
47 #define SR_INT_BIT 2 /* Shift register full/empty */
48 #define CB2_INT_BIT 3
49 #define CB1_INT_BIT 4
50 #define T2_INT_BIT 5 /* Timer 2 interrupt */
51 #define T1_INT_BIT 6 /* Timer 1 interrupt */
52
53 #define CA2_INT BIT(CA2_INT_BIT)
54 #define CA1_INT BIT(CA1_INT_BIT)
55 #define SR_INT BIT(SR_INT_BIT)
56 #define CB2_INT BIT(CB2_INT_BIT)
57 #define CB1_INT BIT(CB1_INT_BIT)
58 #define T2_INT BIT(T2_INT_BIT)
59 #define T1_INT BIT(T1_INT_BIT)
60
61 #define VIA_NUM_INTS 5
62
63 /* Bits in ACR */
64 #define T1MODE 0xc0 /* Timer 1 mode */
65 #define T1MODE_CONT 0x40 /* continuous interrupts */
66
67 /* Bits in PCR */
68 #define CB2_CTRL_MASK 0xe0
69 #define CB2_CTRL_SHIFT 5
70 #define CB1_CTRL_MASK 0x10
71 #define CB1_CTRL_SHIFT 4
72 #define CA2_CTRL_MASK 0x0e
73 #define CA2_CTRL_SHIFT 1
74 #define CA1_CTRL_MASK 0x1
75 #define CA1_CTRL_SHIFT 0
76
77 #define C2_POS 0x2
78 #define C2_IND 0x1
79
80 #define C1_POS 0x1
81
82 /* VIA registers */
83 #define VIA_REG_B 0x00
84 #define VIA_REG_A 0x01
85 #define VIA_REG_DIRB 0x02
86 #define VIA_REG_DIRA 0x03
87 #define VIA_REG_T1CL 0x04
88 #define VIA_REG_T1CH 0x05
89 #define VIA_REG_T1LL 0x06
90 #define VIA_REG_T1LH 0x07
91 #define VIA_REG_T2CL 0x08
92 #define VIA_REG_T2CH 0x09
93 #define VIA_REG_SR 0x0a
94 #define VIA_REG_ACR 0x0b
95 #define VIA_REG_PCR 0x0c
96 #define VIA_REG_IFR 0x0d
97 #define VIA_REG_IER 0x0e
98 #define VIA_REG_ANH 0x0f
99
100 /**
101 * MOS6522Timer:
102 * @counter_value: counter value at load time
103 */
104 typedef struct MOS6522Timer {
105 int index;
106 uint16_t latch;
107 uint16_t counter_value;
108 int64_t load_time;
109 int64_t next_irq_time;
110 uint64_t frequency;
111 QEMUTimer *timer;
112 } MOS6522Timer;
113
114 /**
115 * MOS6522State:
116 * @b: B-side data
117 * @a: A-side data
118 * @dirb: B-side direction (1=output)
119 * @dira: A-side direction (1=output)
120 * @sr: Shift register
121 * @acr: Auxiliary control register
122 * @pcr: Peripheral control register
123 * @ifr: Interrupt flag register
124 * @ier: Interrupt enable register
125 * @anh: A-side data, no handshake
126 * @last_b: last value of B register
127 * @last_acr: last value of ACR register
128 */
129 struct MOS6522State {
130 /*< private >*/
131 SysBusDevice parent_obj;
132 /*< public >*/
133
134 MemoryRegion mem;
135 /* VIA registers */
136 uint8_t b;
137 uint8_t a;
138 uint8_t dirb;
139 uint8_t dira;
140 uint8_t sr;
141 uint8_t acr;
142 uint8_t pcr;
143 uint8_t ifr;
144 uint8_t ier;
145
146 MOS6522Timer timers[2];
147 uint64_t frequency;
148
149 qemu_irq irq;
150 uint8_t last_irq_levels;
151 };
152
153 #define TYPE_MOS6522 "mos6522"
154 OBJECT_DECLARE_TYPE(MOS6522State, MOS6522DeviceClass, MOS6522)
155
156 struct MOS6522DeviceClass {
157 SysBusDeviceClass parent_class;
158
159 ResettablePhases parent_phases;
160 void (*portB_write)(MOS6522State *dev);
161 void (*portA_write)(MOS6522State *dev);
162 /* These are used to influence the CUDA MacOS timebase calibration */
163 uint64_t (*get_timer1_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
164 uint64_t (*get_timer2_counter_value)(MOS6522State *dev, MOS6522Timer *ti);
165 uint64_t (*get_timer1_load_time)(MOS6522State *dev, MOS6522Timer *ti);
166 uint64_t (*get_timer2_load_time)(MOS6522State *dev, MOS6522Timer *ti);
167 };
168
169
170 extern const VMStateDescription vmstate_mos6522;
171
172 uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size);
173 void mos6522_write(void *opaque, hwaddr addr, uint64_t val, unsigned size);
174
175 #endif /* MOS6522_H */