| 1 | /* |
| 2 | * ARM MPS2 SCC emulation |
| 3 | * |
| 4 | * Copyright (c) 2017 Linaro Limited |
| 5 | * Written by Peter Maydell |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License version 2 or |
| 9 | * (at your option) any later version. |
| 10 | */ |
| 11 | |
| 12 | /* |
| 13 | * This is a model of the Serial Communication Controller (SCC) |
| 14 | * block found in most MPS FPGA images. |
| 15 | * |
| 16 | * QEMU interface: |
| 17 | * + sysbus MMIO region 0: the register bank |
| 18 | * + QOM property "scc-cfg4": value of the read-only CFG4 register |
| 19 | * + QOM property "scc-aid": value of the read-only SCC_AID register |
| 20 | * + QOM property "scc-id": value of the read-only SCC_ID register |
| 21 | * + QOM property "scc-cfg0": reset value of the CFG0 register |
| 22 | * + QOM property array "oscclk": reset values of the OSCCLK registers |
| 23 | * (which are accessed via the SYS_CFG channel provided by this device) |
| 24 | * + named GPIO output "remap": this tracks the value of CFG0 register |
| 25 | * bit 0. Boards where this bit controls memory remapping should |
| 26 | * connect this GPIO line to a function performing that mapping. |
| 27 | * Boards where bit 0 has no special function should leave the GPIO |
| 28 | * output disconnected. |
| 29 | */ |
| 30 | #ifndef MPS2_SCC_H |
| 31 | #define MPS2_SCC_H |
| 32 | |
| 33 | #include "hw/core/sysbus.h" |
| 34 | #include "hw/misc/led.h" |
| 35 | #include "qom/object.h" |
| 36 | |
| 37 | #define TYPE_MPS2_SCC "mps2-scc" |
| 38 | OBJECT_DECLARE_SIMPLE_TYPE(MPS2SCC, MPS2_SCC) |
| 39 | |
| 40 | struct MPS2SCC { |
| 41 | /*< private >*/ |
| 42 | SysBusDevice parent_obj; |
| 43 | |
| 44 | /*< public >*/ |
| 45 | MemoryRegion iomem; |
| 46 | LEDState *led[8]; |
| 47 | |
| 48 | uint32_t cfg0; |
| 49 | uint32_t cfg1; |
| 50 | uint32_t cfg2; |
| 51 | uint32_t cfg4; |
| 52 | uint32_t cfg5; |
| 53 | uint32_t cfg6; |
| 54 | uint32_t cfg7; |
| 55 | uint32_t cfgdata_rtn; |
| 56 | uint32_t cfgdata_out; |
| 57 | uint32_t cfgctrl; |
| 58 | uint32_t cfgstat; |
| 59 | uint32_t dll; |
| 60 | uint32_t aid; |
| 61 | uint32_t id; |
| 62 | uint32_t num_oscclk; |
| 63 | uint32_t *oscclk; |
| 64 | uint32_t *oscclk_reset; |
| 65 | uint32_t cfg0_reset; |
| 66 | |
| 67 | qemu_irq remap; |
| 68 | }; |
| 69 | |
| 70 | #endif |