| 1 | /* |
| 2 | * Coherent Manager Global Control Register |
| 3 | * |
| 4 | * Copyright (C) 2015 Imagination Technologies |
| 5 | * |
| 6 | * Copyright (C) 2025 MIPS |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef RISCV_CMGCR_H |
| 13 | #define RISCV_CMGCR_H |
| 14 | |
| 15 | #include "hw/core/sysbus.h" |
| 16 | #include "qom/object.h" |
| 17 | |
| 18 | #define TYPE_RISCV_GCR "riscv-gcr" |
| 19 | OBJECT_DECLARE_SIMPLE_TYPE(RISCVGCRState, RISCV_GCR) |
| 20 | |
| 21 | #define GCR_BASE_ADDR 0x1fb80000ULL |
| 22 | #define GCR_MAX_VPS 256 |
| 23 | |
| 24 | typedef struct RISCVGCRVPState RISCVGCRVPState; |
| 25 | struct RISCVGCRVPState { |
| 26 | uint64_t reset_base; |
| 27 | }; |
| 28 | |
| 29 | typedef struct RISCVGCRState RISCVGCRState; |
| 30 | struct RISCVGCRState { |
| 31 | SysBusDevice parent_obj; |
| 32 | |
| 33 | int32_t gcr_rev; |
| 34 | uint32_t cluster_id; |
| 35 | uint32_t num_vps; |
| 36 | uint32_t num_hart; |
| 37 | uint32_t num_core; |
| 38 | hwaddr gcr_base; |
| 39 | MemoryRegion iomem; |
| 40 | MemoryRegion *cpc_mr; |
| 41 | |
| 42 | uint64_t cpc_base; |
| 43 | |
| 44 | /* VP Local/Other Registers */ |
| 45 | RISCVGCRVPState *vps; |
| 46 | }; |
| 47 | |
| 48 | #endif /* RISCV_CMGCR_H */ |