| 1 | /* |
| 2 | * Cluster Power Controller emulation |
| 3 | * |
| 4 | * Copyright (c) 2016 Imagination Technologies |
| 5 | * |
| 6 | * Copyright (c) 2025 MIPS |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 9 | * |
| 10 | */ |
| 11 | |
| 12 | #ifndef RISCV_CPC_H |
| 13 | #define RISCV_CPC_H |
| 14 | |
| 15 | #include "hw/core/sysbus.h" |
| 16 | #include "qom/object.h" |
| 17 | |
| 18 | #define CPC_ADDRSPACE_SZ 0x6000 |
| 19 | |
| 20 | /* CPC global register offsets relative to base address */ |
| 21 | #define CPC_MTIME_REG_OFS 0x50 |
| 22 | |
| 23 | #define CPC_CM_STAT_CONF_OFS 0x1008 |
| 24 | |
| 25 | /* CPC blocks offsets relative to base address */ |
| 26 | #define CPC_CL_BASE_OFS 0x2000 |
| 27 | #define CPC_CORE_REG_STRIDE 0x100 /* Stride between core-specific registers */ |
| 28 | |
| 29 | /* CPC register offsets relative to block offsets */ |
| 30 | #define CPC_STAT_CONF_OFS 0x08 |
| 31 | #define CPC_VP_STOP_OFS 0x20 |
| 32 | #define CPC_VP_RUN_OFS 0x28 |
| 33 | #define CPC_VP_RUNNING_OFS 0x30 |
| 34 | |
| 35 | #define SEQ_STATE_BIT 19 |
| 36 | #define SEQ_STATE_U5 0x6 |
| 37 | #define SEQ_STATE_U6 0x7 |
| 38 | #define CPC_Cx_STAT_CONF_SEQ_STATE_U5 (SEQ_STATE_U5 << SEQ_STATE_BIT) |
| 39 | #define CPC_Cx_STAT_CONF_SEQ_STATE_U6 (SEQ_STATE_U6 << SEQ_STATE_BIT) |
| 40 | |
| 41 | #define TYPE_RISCV_CPC "xmips-cpc" |
| 42 | OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPCState, RISCV_CPC) |
| 43 | |
| 44 | typedef struct RISCVCPCState { |
| 45 | SysBusDevice parent_obj; |
| 46 | |
| 47 | uint32_t cluster_id; |
| 48 | uint32_t num_vp; |
| 49 | uint32_t num_hart; |
| 50 | uint32_t num_core; |
| 51 | /* VPs running from restart mask */ |
| 52 | uint64_t vps_start_running_mask; |
| 53 | |
| 54 | MemoryRegion mr; |
| 55 | /* Indicates which VPs are in the run state mask */ |
| 56 | uint64_t vps_running_mask; |
| 57 | |
| 58 | /* Array of CPUs managed by this CPC */ |
| 59 | CPUState **cpus; |
| 60 | } RISCVCPCState; |
| 61 | |
| 62 | #define CPC_MAX_VPS 64 /* Maximum number of VPs supported */ |
| 63 | |
| 64 | #endif /* RISCV_CPC_H */ |