| 1 | /* |
| 2 | * QEMU model of the Clock-Reset-LPD (CRL). |
| 3 | * |
| 4 | * Copyright (c) 2022 Xilinx Inc. |
| 5 | * Copyright (c) 2025 Advanced Micro Devices, Inc. |
| 6 | * SPDX-License-Identifier: GPL-2.0-or-later |
| 7 | * |
| 8 | * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com> |
| 9 | */ |
| 10 | #ifndef HW_MISC_XLNX_VERSAL_CRL_H |
| 11 | #define HW_MISC_XLNX_VERSAL_CRL_H |
| 12 | |
| 13 | #include "hw/core/sysbus.h" |
| 14 | #include "hw/core/register.h" |
| 15 | #include "target/arm/cpu-qom.h" |
| 16 | #include "hw/arm/xlnx-versal-version.h" |
| 17 | |
| 18 | #define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base" |
| 19 | #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" |
| 20 | #define TYPE_XLNX_VERSAL2_CRL "xlnx-versal2-crl" |
| 21 | |
| 22 | OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass, |
| 23 | XLNX_VERSAL_CRL_BASE) |
| 24 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) |
| 25 | OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersal2CRL, XLNX_VERSAL2_CRL) |
| 26 | |
| 27 | REG32(ERR_CTRL, 0x0) |
| 28 | FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) |
| 29 | REG32(IR_STATUS, 0x4) |
| 30 | FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) |
| 31 | REG32(IR_MASK, 0x8) |
| 32 | FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) |
| 33 | REG32(IR_ENABLE, 0xc) |
| 34 | FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) |
| 35 | REG32(IR_DISABLE, 0x10) |
| 36 | FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) |
| 37 | REG32(WPROT, 0x1c) |
| 38 | FIELD(WPROT, ACTIVE, 0, 1) |
| 39 | REG32(PLL_CLK_OTHER_DMN, 0x20) |
| 40 | FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) |
| 41 | REG32(RPLL_CTRL, 0x40) |
| 42 | FIELD(RPLL_CTRL, POST_SRC, 24, 3) |
| 43 | FIELD(RPLL_CTRL, PRE_SRC, 20, 3) |
| 44 | FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) |
| 45 | FIELD(RPLL_CTRL, FBDIV, 8, 8) |
| 46 | FIELD(RPLL_CTRL, BYPASS, 3, 1) |
| 47 | FIELD(RPLL_CTRL, RESET, 0, 1) |
| 48 | REG32(RPLL_CFG, 0x44) |
| 49 | FIELD(RPLL_CFG, LOCK_DLY, 25, 7) |
| 50 | FIELD(RPLL_CFG, LOCK_CNT, 13, 10) |
| 51 | FIELD(RPLL_CFG, LFHF, 10, 2) |
| 52 | FIELD(RPLL_CFG, CP, 5, 4) |
| 53 | FIELD(RPLL_CFG, RES, 0, 4) |
| 54 | REG32(RPLL_FRAC_CFG, 0x48) |
| 55 | FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) |
| 56 | FIELD(RPLL_FRAC_CFG, SEED, 22, 3) |
| 57 | FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) |
| 58 | FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) |
| 59 | FIELD(RPLL_FRAC_CFG, DATA, 0, 16) |
| 60 | REG32(PLL_STATUS, 0x50) |
| 61 | FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) |
| 62 | FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) |
| 63 | REG32(RPLL_TO_XPD_CTRL, 0x100) |
| 64 | FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) |
| 65 | FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) |
| 66 | REG32(LPD_TOP_SWITCH_CTRL, 0x104) |
| 67 | FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) |
| 68 | FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) |
| 69 | FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) |
| 70 | FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) |
| 71 | REG32(LPD_LSBUS_CTRL, 0x108) |
| 72 | FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) |
| 73 | FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) |
| 74 | FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) |
| 75 | REG32(CPU_R5_CTRL, 0x10c) |
| 76 | FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) |
| 77 | FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) |
| 78 | FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) |
| 79 | FIELD(CPU_R5_CTRL, CLKACT, 25, 1) |
| 80 | FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) |
| 81 | FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) |
| 82 | REG32(IOU_SWITCH_CTRL, 0x114) |
| 83 | FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) |
| 84 | FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) |
| 85 | FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) |
| 86 | REG32(GEM0_REF_CTRL, 0x118) |
| 87 | FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) |
| 88 | FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) |
| 89 | FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) |
| 90 | FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) |
| 91 | FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) |
| 92 | REG32(GEM1_REF_CTRL, 0x11c) |
| 93 | FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) |
| 94 | FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) |
| 95 | FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) |
| 96 | FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) |
| 97 | FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) |
| 98 | REG32(GEM_TSU_REF_CTRL, 0x120) |
| 99 | FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) |
| 100 | FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) |
| 101 | FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) |
| 102 | REG32(USB0_BUS_REF_CTRL, 0x124) |
| 103 | FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) |
| 104 | FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) |
| 105 | FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) |
| 106 | REG32(UART0_REF_CTRL, 0x128) |
| 107 | FIELD(UART0_REF_CTRL, CLKACT, 25, 1) |
| 108 | FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) |
| 109 | FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) |
| 110 | REG32(UART1_REF_CTRL, 0x12c) |
| 111 | FIELD(UART1_REF_CTRL, CLKACT, 25, 1) |
| 112 | FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) |
| 113 | FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) |
| 114 | REG32(SPI0_REF_CTRL, 0x130) |
| 115 | FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) |
| 116 | FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) |
| 117 | FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) |
| 118 | REG32(SPI1_REF_CTRL, 0x134) |
| 119 | FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) |
| 120 | FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) |
| 121 | FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) |
| 122 | REG32(CAN0_REF_CTRL, 0x138) |
| 123 | FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) |
| 124 | FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) |
| 125 | FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) |
| 126 | REG32(CAN1_REF_CTRL, 0x13c) |
| 127 | FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) |
| 128 | FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) |
| 129 | FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) |
| 130 | REG32(I2C0_REF_CTRL, 0x140) |
| 131 | FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) |
| 132 | FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) |
| 133 | FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) |
| 134 | REG32(I2C1_REF_CTRL, 0x144) |
| 135 | FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) |
| 136 | FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) |
| 137 | FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) |
| 138 | REG32(DBG_LPD_CTRL, 0x148) |
| 139 | FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) |
| 140 | FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) |
| 141 | FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) |
| 142 | REG32(TIMESTAMP_REF_CTRL, 0x14c) |
| 143 | FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) |
| 144 | FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) |
| 145 | FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) |
| 146 | REG32(CRL_SAFETY_CHK, 0x150) |
| 147 | REG32(PSM_REF_CTRL, 0x154) |
| 148 | FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) |
| 149 | FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) |
| 150 | REG32(DBG_TSTMP_CTRL, 0x158) |
| 151 | FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) |
| 152 | FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) |
| 153 | FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) |
| 154 | REG32(CPM_TOPSW_REF_CTRL, 0x15c) |
| 155 | FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) |
| 156 | FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) |
| 157 | FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) |
| 158 | REG32(USB3_DUAL_REF_CTRL, 0x160) |
| 159 | FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) |
| 160 | FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) |
| 161 | FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) |
| 162 | REG32(RST_CPU_R5, 0x300) |
| 163 | FIELD(RST_CPU_R5, RESET_PGE, 4, 1) |
| 164 | FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) |
| 165 | FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) |
| 166 | FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) |
| 167 | REG32(RST_ADMA, 0x304) |
| 168 | FIELD(RST_ADMA, RESET, 0, 1) |
| 169 | REG32(RST_GEM0, 0x308) |
| 170 | FIELD(RST_GEM0, RESET, 0, 1) |
| 171 | REG32(RST_GEM1, 0x30c) |
| 172 | FIELD(RST_GEM1, RESET, 0, 1) |
| 173 | REG32(RST_SPARE, 0x310) |
| 174 | FIELD(RST_SPARE, RESET, 0, 1) |
| 175 | REG32(RST_USB0, 0x314) |
| 176 | FIELD(RST_USB0, RESET, 0, 1) |
| 177 | REG32(RST_UART0, 0x318) |
| 178 | FIELD(RST_UART0, RESET, 0, 1) |
| 179 | REG32(RST_UART1, 0x31c) |
| 180 | FIELD(RST_UART1, RESET, 0, 1) |
| 181 | REG32(RST_SPI0, 0x320) |
| 182 | FIELD(RST_SPI0, RESET, 0, 1) |
| 183 | REG32(RST_SPI1, 0x324) |
| 184 | FIELD(RST_SPI1, RESET, 0, 1) |
| 185 | REG32(RST_CAN0, 0x328) |
| 186 | FIELD(RST_CAN0, RESET, 0, 1) |
| 187 | REG32(RST_CAN1, 0x32c) |
| 188 | FIELD(RST_CAN1, RESET, 0, 1) |
| 189 | REG32(RST_I2C0, 0x330) |
| 190 | FIELD(RST_I2C0, RESET, 0, 1) |
| 191 | REG32(RST_I2C1, 0x334) |
| 192 | FIELD(RST_I2C1, RESET, 0, 1) |
| 193 | REG32(RST_DBG_LPD, 0x338) |
| 194 | FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) |
| 195 | FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) |
| 196 | FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) |
| 197 | FIELD(RST_DBG_LPD, RESET, 0, 1) |
| 198 | REG32(RST_GPIO, 0x33c) |
| 199 | FIELD(RST_GPIO, RESET, 0, 1) |
| 200 | REG32(RST_TTC, 0x344) |
| 201 | FIELD(RST_TTC, TTC3_RESET, 3, 1) |
| 202 | FIELD(RST_TTC, TTC2_RESET, 2, 1) |
| 203 | FIELD(RST_TTC, TTC1_RESET, 1, 1) |
| 204 | FIELD(RST_TTC, TTC0_RESET, 0, 1) |
| 205 | REG32(RST_TIMESTAMP, 0x348) |
| 206 | FIELD(RST_TIMESTAMP, RESET, 0, 1) |
| 207 | REG32(RST_SWDT, 0x34c) |
| 208 | FIELD(RST_SWDT, RESET, 0, 1) |
| 209 | REG32(RST_OCM, 0x350) |
| 210 | FIELD(RST_OCM, RESET, 0, 1) |
| 211 | REG32(RST_IPI, 0x354) |
| 212 | FIELD(RST_IPI, RESET, 0, 1) |
| 213 | REG32(RST_SYSMON, 0x358) |
| 214 | FIELD(RST_SYSMON, SEQ_RST, 1, 1) |
| 215 | FIELD(RST_SYSMON, CFG_RST, 0, 1) |
| 216 | REG32(RST_FPD, 0x360) |
| 217 | FIELD(RST_FPD, SRST, 1, 1) |
| 218 | FIELD(RST_FPD, POR, 0, 1) |
| 219 | REG32(PSM_RST_MODE, 0x370) |
| 220 | FIELD(PSM_RST_MODE, WAKEUP, 2, 1) |
| 221 | FIELD(PSM_RST_MODE, RST_MODE, 0, 2) |
| 222 | |
| 223 | #define CRL_R_MAX (R_PSM_RST_MODE + 1) |
| 224 | |
| 225 | REG32(VERSAL2_ERR_CTRL, 0x0) |
| 226 | REG32(VERSAL2_WPROT, 0x1c) |
| 227 | FIELD(VERSAL2_WPROT, ACTIVE, 0, 1) |
| 228 | REG32(VERSAL2_RPLL_CTRL, 0x40) |
| 229 | FIELD(VERSAL2_RPLL_CTRL, POST_SRC, 24, 3) |
| 230 | FIELD(VERSAL2_RPLL_CTRL, PRE_SRC, 20, 3) |
| 231 | FIELD(VERSAL2_RPLL_CTRL, CLKOUTDIV, 16, 2) |
| 232 | FIELD(VERSAL2_RPLL_CTRL, FBDIV, 8, 8) |
| 233 | FIELD(VERSAL2_RPLL_CTRL, BYPASS, 3, 1) |
| 234 | FIELD(VERSAL2_RPLL_CTRL, RESET, 0, 1) |
| 235 | REG32(VERSAL2_RPLL_CFG, 0x44) |
| 236 | FIELD(VERSAL2_RPLL_CFG, LOCK_DLY, 25, 7) |
| 237 | FIELD(VERSAL2_RPLL_CFG, LOCK_CNT, 13, 10) |
| 238 | FIELD(VERSAL2_RPLL_CFG, LFHF, 10, 2) |
| 239 | FIELD(VERSAL2_RPLL_CFG, CP, 5, 4) |
| 240 | FIELD(VERSAL2_RPLL_CFG, RES, 0, 4) |
| 241 | REG32(VERSAL2_FLXPLL_CTRL, 0x50) |
| 242 | FIELD(VERSAL2_FLXPLL_CTRL, POST_SRC, 24, 3) |
| 243 | FIELD(VERSAL2_FLXPLL_CTRL, PRE_SRC, 20, 3) |
| 244 | FIELD(VERSAL2_FLXPLL_CTRL, CLKOUTDIV, 16, 2) |
| 245 | FIELD(VERSAL2_FLXPLL_CTRL, FBDIV, 8, 8) |
| 246 | FIELD(VERSAL2_FLXPLL_CTRL, BYPASS, 3, 1) |
| 247 | FIELD(VERSAL2_FLXPLL_CTRL, RESET, 0, 1) |
| 248 | REG32(VERSAL2_FLXPLL_CFG, 0x54) |
| 249 | FIELD(VERSAL2_FLXPLL_CFG, LOCK_DLY, 25, 7) |
| 250 | FIELD(VERSAL2_FLXPLL_CFG, LOCK_CNT, 13, 10) |
| 251 | FIELD(VERSAL2_FLXPLL_CFG, LFHF, 10, 2) |
| 252 | FIELD(VERSAL2_FLXPLL_CFG, CP, 5, 4) |
| 253 | FIELD(VERSAL2_FLXPLL_CFG, RES, 0, 4) |
| 254 | REG32(VERSAL2_PLL_STATUS, 0x60) |
| 255 | FIELD(VERSAL2_PLL_STATUS, FLXPLL_STABLE, 3, 1) |
| 256 | FIELD(VERSAL2_PLL_STATUS, RPLL_STABLE, 2, 1) |
| 257 | FIELD(VERSAL2_PLL_STATUS, FLXPLL_LOCK, 1, 1) |
| 258 | FIELD(VERSAL2_PLL_STATUS, RPLL_LOCK, 0, 1) |
| 259 | REG32(VERSAL2_RPLL_TO_XPD_CTRL, 0x100) |
| 260 | FIELD(VERSAL2_RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) |
| 261 | REG32(VERSAL2_LPX_TOP_SWITCH_CTRL, 0x104) |
| 262 | FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) |
| 263 | FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, CLKACT, 25, 1) |
| 264 | FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) |
| 265 | FIELD(VERSAL2_LPX_TOP_SWITCH_CTRL, SRCSEL, 0, 3) |
| 266 | REG32(VERSAL2_LPX_LSBUS_CLK_CTRL, 0x108) |
| 267 | FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, CLKACT, 25, 1) |
| 268 | FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, DIVISOR0, 8, 10) |
| 269 | FIELD(VERSAL2_LPX_LSBUS_CLK_CTRL, SRCSEL, 0, 3) |
| 270 | REG32(VERSAL2_RPU_CLK_CTRL, 0x10c) |
| 271 | FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT, 25, 1) |
| 272 | FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERE, 24, 1) |
| 273 | FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERD, 23, 1) |
| 274 | FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERC, 22, 1) |
| 275 | FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERB, 21, 1) |
| 276 | FIELD(VERSAL2_RPU_CLK_CTRL, CLKACT_CLUSTERA, 20, 1) |
| 277 | FIELD(VERSAL2_RPU_CLK_CTRL, DIVISOR0, 8, 10) |
| 278 | FIELD(VERSAL2_RPU_CLK_CTRL, SRCSEL, 0, 3) |
| 279 | REG32(VERSAL2_OCM_CLK_CTRL, 0x120) |
| 280 | FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM3, 24, 1) |
| 281 | FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM2, 23, 1) |
| 282 | FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM1, 22, 1) |
| 283 | FIELD(VERSAL2_OCM_CLK_CTRL, CLKACT_OCM0, 21, 1) |
| 284 | REG32(VERSAL2_IOU_SWITCH_CLK_CTRL, 0x124) |
| 285 | FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, CLKACT, 25, 1) |
| 286 | FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, DIVISOR0, 8, 10) |
| 287 | FIELD(VERSAL2_IOU_SWITCH_CLK_CTRL, SRCSEL, 0, 3) |
| 288 | REG32(VERSAL2_GEM0_REF_CTRL, 0x128) |
| 289 | FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_RX, 27, 1) |
| 290 | FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT_TX, 26, 1) |
| 291 | FIELD(VERSAL2_GEM0_REF_CTRL, CLKACT, 25, 1) |
| 292 | FIELD(VERSAL2_GEM0_REF_CTRL, DIVISOR0, 8, 10) |
| 293 | FIELD(VERSAL2_GEM0_REF_CTRL, SRCSEL, 0, 3) |
| 294 | REG32(VERSAL2_GEM1_REF_CTRL, 0x12c) |
| 295 | FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_RX, 27, 1) |
| 296 | FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT_TX, 26, 1) |
| 297 | FIELD(VERSAL2_GEM1_REF_CTRL, CLKACT, 25, 1) |
| 298 | FIELD(VERSAL2_GEM1_REF_CTRL, DIVISOR0, 8, 10) |
| 299 | FIELD(VERSAL2_GEM1_REF_CTRL, SRCSEL, 0, 3) |
| 300 | REG32(VERSAL2_GEM_TSU_REF_CLK_CTRL, 0x130) |
| 301 | FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, CLKACT, 25, 1) |
| 302 | FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 303 | FIELD(VERSAL2_GEM_TSU_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 304 | REG32(VERSAL2_USB0_BUS_REF_CLK_CTRL, 0x134) |
| 305 | FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, CLKACT, 25, 1) |
| 306 | FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 307 | FIELD(VERSAL2_USB0_BUS_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 308 | REG32(VERSAL2_USB1_BUS_REF_CLK_CTRL, 0x138) |
| 309 | FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, CLKACT, 25, 1) |
| 310 | FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 311 | FIELD(VERSAL2_USB1_BUS_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 312 | REG32(VERSAL2_UART0_REF_CLK_CTRL, 0x13c) |
| 313 | FIELD(VERSAL2_UART0_REF_CLK_CTRL, CLKACT, 25, 1) |
| 314 | FIELD(VERSAL2_UART0_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 315 | FIELD(VERSAL2_UART0_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 316 | REG32(VERSAL2_UART1_REF_CLK_CTRL, 0x140) |
| 317 | FIELD(VERSAL2_UART1_REF_CLK_CTRL, CLKACT, 25, 1) |
| 318 | FIELD(VERSAL2_UART1_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 319 | FIELD(VERSAL2_UART1_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 320 | REG32(VERSAL2_SPI0_REF_CLK_CTRL, 0x144) |
| 321 | FIELD(VERSAL2_SPI0_REF_CLK_CTRL, CLKACT, 25, 1) |
| 322 | FIELD(VERSAL2_SPI0_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 323 | FIELD(VERSAL2_SPI0_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 324 | REG32(VERSAL2_SPI1_REF_CLK_CTRL, 0x148) |
| 325 | FIELD(VERSAL2_SPI1_REF_CLK_CTRL, CLKACT, 25, 1) |
| 326 | FIELD(VERSAL2_SPI1_REF_CLK_CTRL, DIVISOR0, 8, 10) |
| 327 | FIELD(VERSAL2_SPI1_REF_CLK_CTRL, SRCSEL, 0, 3) |
| 328 | REG32(VERSAL2_CAN0_REF_2X_CTRL, 0x14c) |
| 329 | FIELD(VERSAL2_CAN0_REF_2X_CTRL, CLKACT, 25, 1) |
| 330 | FIELD(VERSAL2_CAN0_REF_2X_CTRL, DIVISOR0, 8, 10) |
| 331 | FIELD(VERSAL2_CAN0_REF_2X_CTRL, SRCSEL, 0, 3) |
| 332 | REG32(VERSAL2_CAN1_REF_2X_CTRL, 0x150) |
| 333 | FIELD(VERSAL2_CAN1_REF_2X_CTRL, CLKACT, 25, 1) |
| 334 | FIELD(VERSAL2_CAN1_REF_2X_CTRL, DIVISOR0, 8, 10) |
| 335 | FIELD(VERSAL2_CAN1_REF_2X_CTRL, SRCSEL, 0, 3) |
| 336 | REG32(VERSAL2_CAN2_REF_2X_CTRL, 0x154) |
| 337 | FIELD(VERSAL2_CAN2_REF_2X_CTRL, CLKACT, 25, 1) |
| 338 | FIELD(VERSAL2_CAN2_REF_2X_CTRL, DIVISOR0, 8, 10) |
| 339 | FIELD(VERSAL2_CAN2_REF_2X_CTRL, SRCSEL, 0, 3) |
| 340 | REG32(VERSAL2_CAN3_REF_2X_CTRL, 0x158) |
| 341 | FIELD(VERSAL2_CAN3_REF_2X_CTRL, CLKACT, 25, 1) |
| 342 | FIELD(VERSAL2_CAN3_REF_2X_CTRL, DIVISOR0, 8, 10) |
| 343 | FIELD(VERSAL2_CAN3_REF_2X_CTRL, SRCSEL, 0, 3) |
| 344 | REG32(VERSAL2_I3C0_REF_CTRL, 0x15c) |
| 345 | FIELD(VERSAL2_I3C0_REF_CTRL, CLKACT, 25, 1) |
| 346 | FIELD(VERSAL2_I3C0_REF_CTRL, DIVISOR0, 8, 10) |
| 347 | FIELD(VERSAL2_I3C0_REF_CTRL, SRCSEL, 0, 3) |
| 348 | REG32(VERSAL2_I3C1_REF_CTRL, 0x160) |
| 349 | FIELD(VERSAL2_I3C1_REF_CTRL, CLKACT, 25, 1) |
| 350 | FIELD(VERSAL2_I3C1_REF_CTRL, DIVISOR0, 8, 10) |
| 351 | FIELD(VERSAL2_I3C1_REF_CTRL, SRCSEL, 0, 3) |
| 352 | REG32(VERSAL2_I3C2_REF_CTRL, 0x164) |
| 353 | FIELD(VERSAL2_I3C2_REF_CTRL, CLKACT, 25, 1) |
| 354 | FIELD(VERSAL2_I3C2_REF_CTRL, DIVISOR0, 8, 10) |
| 355 | FIELD(VERSAL2_I3C2_REF_CTRL, SRCSEL, 0, 3) |
| 356 | REG32(VERSAL2_I3C3_REF_CTRL, 0x168) |
| 357 | FIELD(VERSAL2_I3C3_REF_CTRL, CLKACT, 25, 1) |
| 358 | FIELD(VERSAL2_I3C3_REF_CTRL, DIVISOR0, 8, 10) |
| 359 | FIELD(VERSAL2_I3C3_REF_CTRL, SRCSEL, 0, 3) |
| 360 | REG32(VERSAL2_I3C4_REF_CTRL, 0x16c) |
| 361 | FIELD(VERSAL2_I3C4_REF_CTRL, CLKACT, 25, 1) |
| 362 | FIELD(VERSAL2_I3C4_REF_CTRL, DIVISOR0, 8, 10) |
| 363 | FIELD(VERSAL2_I3C4_REF_CTRL, SRCSEL, 0, 3) |
| 364 | REG32(VERSAL2_I3C5_REF_CTRL, 0x170) |
| 365 | FIELD(VERSAL2_I3C5_REF_CTRL, CLKACT, 25, 1) |
| 366 | FIELD(VERSAL2_I3C5_REF_CTRL, DIVISOR0, 8, 10) |
| 367 | FIELD(VERSAL2_I3C5_REF_CTRL, SRCSEL, 0, 3) |
| 368 | REG32(VERSAL2_I3C6_REF_CTRL, 0x174) |
| 369 | FIELD(VERSAL2_I3C6_REF_CTRL, CLKACT, 25, 1) |
| 370 | FIELD(VERSAL2_I3C6_REF_CTRL, DIVISOR0, 8, 10) |
| 371 | FIELD(VERSAL2_I3C6_REF_CTRL, SRCSEL, 0, 3) |
| 372 | REG32(VERSAL2_I3C7_REF_CTRL, 0x178) |
| 373 | FIELD(VERSAL2_I3C7_REF_CTRL, CLKACT, 25, 1) |
| 374 | FIELD(VERSAL2_I3C7_REF_CTRL, DIVISOR0, 8, 10) |
| 375 | FIELD(VERSAL2_I3C7_REF_CTRL, SRCSEL, 0, 3) |
| 376 | REG32(VERSAL2_DBG_LPX_CTRL, 0x17c) |
| 377 | FIELD(VERSAL2_DBG_LPX_CTRL, CLKACT, 25, 1) |
| 378 | FIELD(VERSAL2_DBG_LPX_CTRL, DIVISOR0, 8, 10) |
| 379 | FIELD(VERSAL2_DBG_LPX_CTRL, SRCSEL, 0, 3) |
| 380 | REG32(VERSAL2_TIMESTAMP_REF_CTRL, 0x180) |
| 381 | FIELD(VERSAL2_TIMESTAMP_REF_CTRL, CLKACT, 25, 1) |
| 382 | FIELD(VERSAL2_TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) |
| 383 | FIELD(VERSAL2_TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) |
| 384 | REG32(VERSAL2_SAFETY_CHK, 0x184) |
| 385 | REG32(VERSAL2_ASU_CLK_CTRL, 0x188) |
| 386 | FIELD(VERSAL2_ASU_CLK_CTRL, DIVISOR0, 8, 10) |
| 387 | FIELD(VERSAL2_ASU_CLK_CTRL, SRCSEL, 0, 3) |
| 388 | REG32(VERSAL2_DBG_TSTMP_CLK_CTRL, 0x18c) |
| 389 | FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, CLKACT, 25, 1) |
| 390 | FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, DIVISOR0, 8, 10) |
| 391 | FIELD(VERSAL2_DBG_TSTMP_CLK_CTRL, SRCSEL, 0, 3) |
| 392 | REG32(VERSAL2_MMI_TOPSW_CLK_CTRL, 0x190) |
| 393 | FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, CLKACT, 25, 1) |
| 394 | FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, DIVISOR0, 8, 10) |
| 395 | FIELD(VERSAL2_MMI_TOPSW_CLK_CTRL, SRCSEL, 0, 3) |
| 396 | REG32(VERSAL2_WWDT_PLL_CLK_CTRL, 0x194) |
| 397 | FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, DIVISOR0, 8, 10) |
| 398 | FIELD(VERSAL2_WWDT_PLL_CLK_CTRL, SRCSEL, 0, 3) |
| 399 | REG32(VERSAL2_RCLK_CTRL, 0x1a0) |
| 400 | FIELD(VERSAL2_RCLK_CTRL, CLKACT, 8, 6) |
| 401 | FIELD(VERSAL2_RCLK_CTRL, SELECT, 0, 6) |
| 402 | REG32(VERSAL2_RST_RPU_A, 0x310) |
| 403 | FIELD(VERSAL2_RST_RPU_A, TOPRESET, 16, 1) |
| 404 | FIELD(VERSAL2_RST_RPU_A, CORE1_POR, 9, 1) |
| 405 | FIELD(VERSAL2_RST_RPU_A, CORE0_POR, 8, 1) |
| 406 | FIELD(VERSAL2_RST_RPU_A, CORE1_RESET, 1, 1) |
| 407 | FIELD(VERSAL2_RST_RPU_A, CORE0_RESET, 0, 1) |
| 408 | REG32(VERSAL2_RST_RPU_B, 0x314) |
| 409 | FIELD(VERSAL2_RST_RPU_B, TOPRESET, 16, 1) |
| 410 | FIELD(VERSAL2_RST_RPU_B, CORE1_POR, 9, 1) |
| 411 | FIELD(VERSAL2_RST_RPU_B, CORE0_POR, 8, 1) |
| 412 | FIELD(VERSAL2_RST_RPU_B, CORE1_RESET, 1, 1) |
| 413 | FIELD(VERSAL2_RST_RPU_B, CORE0_RESET, 0, 1) |
| 414 | REG32(VERSAL2_RST_RPU_C, 0x318) |
| 415 | FIELD(VERSAL2_RST_RPU_C, TOPRESET, 16, 1) |
| 416 | FIELD(VERSAL2_RST_RPU_C, CORE1_POR, 9, 1) |
| 417 | FIELD(VERSAL2_RST_RPU_C, CORE0_POR, 8, 1) |
| 418 | FIELD(VERSAL2_RST_RPU_C, CORE1_RESET, 1, 1) |
| 419 | FIELD(VERSAL2_RST_RPU_C, CORE0_RESET, 0, 1) |
| 420 | REG32(VERSAL2_RST_RPU_D, 0x31c) |
| 421 | FIELD(VERSAL2_RST_RPU_D, TOPRESET, 16, 1) |
| 422 | FIELD(VERSAL2_RST_RPU_D, CORE1_POR, 9, 1) |
| 423 | FIELD(VERSAL2_RST_RPU_D, CORE0_POR, 8, 1) |
| 424 | FIELD(VERSAL2_RST_RPU_D, CORE1_RESET, 1, 1) |
| 425 | FIELD(VERSAL2_RST_RPU_D, CORE0_RESET, 0, 1) |
| 426 | REG32(VERSAL2_RST_RPU_E, 0x320) |
| 427 | FIELD(VERSAL2_RST_RPU_E, TOPRESET, 16, 1) |
| 428 | FIELD(VERSAL2_RST_RPU_E, CORE1_POR, 9, 1) |
| 429 | FIELD(VERSAL2_RST_RPU_E, CORE0_POR, 8, 1) |
| 430 | FIELD(VERSAL2_RST_RPU_E, CORE1_RESET, 1, 1) |
| 431 | FIELD(VERSAL2_RST_RPU_E, CORE0_RESET, 0, 1) |
| 432 | REG32(VERSAL2_RST_RPU_GD_0, 0x324) |
| 433 | FIELD(VERSAL2_RST_RPU_GD_0, RESET, 1, 1) |
| 434 | FIELD(VERSAL2_RST_RPU_GD_0, TOP_RESET, 0, 1) |
| 435 | REG32(VERSAL2_RST_RPU_GD_1, 0x328) |
| 436 | FIELD(VERSAL2_RST_RPU_GD_1, RESET, 1, 1) |
| 437 | FIELD(VERSAL2_RST_RPU_GD_1, TOP_RESET, 0, 1) |
| 438 | REG32(VERSAL2_RST_ASU_GD, 0x32c) |
| 439 | FIELD(VERSAL2_RST_ASU_GD, RESET, 1, 1) |
| 440 | FIELD(VERSAL2_RST_ASU_GD, TOP_RESET, 0, 1) |
| 441 | REG32(VERSAL2_RST_ADMA, 0x334) |
| 442 | FIELD(VERSAL2_RST_ADMA, RESET, 0, 1) |
| 443 | REG32(VERSAL2_RST_SDMA, 0x338) |
| 444 | FIELD(VERSAL2_RST_SDMA, RESET, 0, 1) |
| 445 | REG32(VERSAL2_RST_GEM0, 0x33c) |
| 446 | FIELD(VERSAL2_RST_GEM0, RESET, 0, 1) |
| 447 | REG32(VERSAL2_RST_GEM1, 0x340) |
| 448 | FIELD(VERSAL2_RST_GEM1, RESET, 0, 1) |
| 449 | REG32(VERSAL2_RST_USB0, 0x348) |
| 450 | FIELD(VERSAL2_RST_USB0, RESET, 0, 1) |
| 451 | REG32(VERSAL2_RST_USB1, 0x34c) |
| 452 | FIELD(VERSAL2_RST_USB1, RESET, 0, 1) |
| 453 | REG32(VERSAL2_RST_UART0, 0x350) |
| 454 | FIELD(VERSAL2_RST_UART0, RESET, 0, 1) |
| 455 | REG32(VERSAL2_RST_UART1, 0x354) |
| 456 | FIELD(VERSAL2_RST_UART1, RESET, 0, 1) |
| 457 | REG32(VERSAL2_RST_SPI0, 0x358) |
| 458 | FIELD(VERSAL2_RST_SPI0, RESET, 0, 1) |
| 459 | REG32(VERSAL2_RST_SPI1, 0x35c) |
| 460 | FIELD(VERSAL2_RST_SPI1, RESET, 0, 1) |
| 461 | REG32(VERSAL2_RST_CAN0, 0x360) |
| 462 | FIELD(VERSAL2_RST_CAN0, RESET, 0, 1) |
| 463 | REG32(VERSAL2_RST_CAN1, 0x364) |
| 464 | FIELD(VERSAL2_RST_CAN1, RESET, 0, 1) |
| 465 | REG32(VERSAL2_RST_CAN2, 0x368) |
| 466 | FIELD(VERSAL2_RST_CAN2, RESET, 0, 1) |
| 467 | REG32(VERSAL2_RST_CAN3, 0x36c) |
| 468 | FIELD(VERSAL2_RST_CAN3, RESET, 0, 1) |
| 469 | REG32(VERSAL2_RST_I3C0, 0x374) |
| 470 | FIELD(VERSAL2_RST_I3C0, RESET, 0, 1) |
| 471 | REG32(VERSAL2_RST_I3C1, 0x378) |
| 472 | FIELD(VERSAL2_RST_I3C1, RESET, 0, 1) |
| 473 | REG32(VERSAL2_RST_I3C2, 0x37c) |
| 474 | FIELD(VERSAL2_RST_I3C2, RESET, 0, 1) |
| 475 | REG32(VERSAL2_RST_I3C3, 0x380) |
| 476 | FIELD(VERSAL2_RST_I3C3, RESET, 0, 1) |
| 477 | REG32(VERSAL2_RST_I3C4, 0x384) |
| 478 | FIELD(VERSAL2_RST_I3C4, RESET, 0, 1) |
| 479 | REG32(VERSAL2_RST_I3C5, 0x388) |
| 480 | FIELD(VERSAL2_RST_I3C5, RESET, 0, 1) |
| 481 | REG32(VERSAL2_RST_I3C6, 0x38c) |
| 482 | FIELD(VERSAL2_RST_I3C6, RESET, 0, 1) |
| 483 | REG32(VERSAL2_RST_I3C7, 0x390) |
| 484 | FIELD(VERSAL2_RST_I3C7, RESET, 0, 1) |
| 485 | REG32(VERSAL2_RST_DBG_LPX, 0x398) |
| 486 | FIELD(VERSAL2_RST_DBG_LPX, RESET_HSDP, 1, 1) |
| 487 | FIELD(VERSAL2_RST_DBG_LPX, RESET, 0, 1) |
| 488 | REG32(VERSAL2_RST_GPIO, 0x39c) |
| 489 | FIELD(VERSAL2_RST_GPIO, RESET, 0, 1) |
| 490 | REG32(VERSAL2_RST_TTC, 0x3a0) |
| 491 | FIELD(VERSAL2_RST_TTC, TTC7_RESET, 7, 1) |
| 492 | FIELD(VERSAL2_RST_TTC, TTC6_RESET, 6, 1) |
| 493 | FIELD(VERSAL2_RST_TTC, TTC5_RESET, 5, 1) |
| 494 | FIELD(VERSAL2_RST_TTC, TTC4_RESET, 4, 1) |
| 495 | FIELD(VERSAL2_RST_TTC, TTC3_RESET, 3, 1) |
| 496 | FIELD(VERSAL2_RST_TTC, TTC2_RESET, 2, 1) |
| 497 | FIELD(VERSAL2_RST_TTC, TTC1_RESET, 1, 1) |
| 498 | FIELD(VERSAL2_RST_TTC, TTC0_RESET, 0, 1) |
| 499 | REG32(VERSAL2_RST_TIMESTAMP, 0x3a4) |
| 500 | FIELD(VERSAL2_RST_TIMESTAMP, RESET, 0, 1) |
| 501 | REG32(VERSAL2_RST_SWDT0, 0x3a8) |
| 502 | FIELD(VERSAL2_RST_SWDT0, RESET, 0, 1) |
| 503 | REG32(VERSAL2_RST_SWDT1, 0x3ac) |
| 504 | FIELD(VERSAL2_RST_SWDT1, RESET, 0, 1) |
| 505 | REG32(VERSAL2_RST_SWDT2, 0x3b0) |
| 506 | FIELD(VERSAL2_RST_SWDT2, RESET, 0, 1) |
| 507 | REG32(VERSAL2_RST_SWDT3, 0x3b4) |
| 508 | FIELD(VERSAL2_RST_SWDT3, RESET, 0, 1) |
| 509 | REG32(VERSAL2_RST_SWDT4, 0x3b8) |
| 510 | FIELD(VERSAL2_RST_SWDT4, RESET, 0, 1) |
| 511 | REG32(VERSAL2_RST_IPI, 0x3bc) |
| 512 | FIELD(VERSAL2_RST_IPI, RESET, 0, 1) |
| 513 | REG32(VERSAL2_RST_SYSMON, 0x3c0) |
| 514 | FIELD(VERSAL2_RST_SYSMON, CFG_RST, 0, 1) |
| 515 | REG32(VERSAL2_ASU_MB_RST_MODE, 0x3c4) |
| 516 | FIELD(VERSAL2_ASU_MB_RST_MODE, WAKEUP, 2, 1) |
| 517 | FIELD(VERSAL2_ASU_MB_RST_MODE, RST_MODE, 0, 2) |
| 518 | REG32(VERSAL2_FPX_TOPSW_MUX_CTRL, 0x3c8) |
| 519 | FIELD(VERSAL2_FPX_TOPSW_MUX_CTRL, SELECT, 0, 1) |
| 520 | REG32(VERSAL2_RST_FPX, 0x3d0) |
| 521 | FIELD(VERSAL2_RST_FPX, SRST, 1, 1) |
| 522 | FIELD(VERSAL2_RST_FPX, POR, 0, 1) |
| 523 | REG32(VERSAL2_RST_MMI, 0x3d4) |
| 524 | FIELD(VERSAL2_RST_MMI, POR, 0, 1) |
| 525 | REG32(VERSAL2_RST_OCM, 0x3d8) |
| 526 | FIELD(VERSAL2_RST_OCM, RESET_OCM3, 3, 1) |
| 527 | FIELD(VERSAL2_RST_OCM, RESET_OCM2, 2, 1) |
| 528 | FIELD(VERSAL2_RST_OCM, RESET_OCM1, 1, 1) |
| 529 | FIELD(VERSAL2_RST_OCM, RESET_OCM0, 0, 1) |
| 530 | |
| 531 | #define VERSAL2_CRL_R_MAX (R_VERSAL2_RST_OCM + 1) |
| 532 | |
| 533 | struct XlnxVersalCRLBase { |
| 534 | SysBusDevice parent_obj; |
| 535 | |
| 536 | uint32_t *regs; |
| 537 | }; |
| 538 | |
| 539 | struct XlnxVersalCRLBaseClass { |
| 540 | SysBusDeviceClass parent_class; |
| 541 | |
| 542 | DeviceState ** (*decode_periph_rst)(XlnxVersalCRLBase *s, hwaddr, size_t *); |
| 543 | }; |
| 544 | |
| 545 | struct XlnxVersalCRL { |
| 546 | XlnxVersalCRLBase parent_obj; |
| 547 | qemu_irq irq; |
| 548 | |
| 549 | struct { |
| 550 | DeviceState *rpu[2]; |
| 551 | DeviceState *adma[8]; |
| 552 | DeviceState *uart[2]; |
| 553 | DeviceState *gem[2]; |
| 554 | DeviceState *usb[1]; |
| 555 | } cfg; |
| 556 | |
| 557 | uint32_t regs[CRL_R_MAX]; |
| 558 | RegisterInfo regs_info[CRL_R_MAX]; |
| 559 | }; |
| 560 | |
| 561 | struct XlnxVersal2CRL { |
| 562 | XlnxVersalCRLBase parent_obj; |
| 563 | |
| 564 | struct { |
| 565 | DeviceState *rpu[10]; |
| 566 | DeviceState *adma[8]; |
| 567 | DeviceState *sdma[8]; |
| 568 | DeviceState *uart[2]; |
| 569 | DeviceState *gem[2]; |
| 570 | DeviceState *usb[2]; |
| 571 | DeviceState *can[4]; |
| 572 | } cfg; |
| 573 | |
| 574 | RegisterInfo regs_info[VERSAL2_CRL_R_MAX]; |
| 575 | uint32_t regs[VERSAL2_CRL_R_MAX]; |
| 576 | }; |
| 577 | |
| 578 | static inline const char *xlnx_versal_crl_class_name(VersalVersion ver) |
| 579 | { |
| 580 | switch (ver) { |
| 581 | case VERSAL_VER_VERSAL: |
| 582 | return TYPE_XLNX_VERSAL_CRL; |
| 583 | case VERSAL_VER_VERSAL2: |
| 584 | return TYPE_XLNX_VERSAL2_CRL; |
| 585 | default: |
| 586 | g_assert_not_reached(); |
| 587 | } |
| 588 | } |
| 589 | |
| 590 | #endif |